From: Dan Williams <dan.j.williams@intel.com>
To: "Weiny, Ira" <ira.weiny@intel.com>
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
linux-cxl@vger.kernel.org,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH V3.1] cxl/mem: Map registers based on capabilities
Date: Sat, 5 Jun 2021 17:30:30 -0700 [thread overview]
Message-ID: <CAPcyv4jrdGAtaoArXEQAH5XPrGQxCraiMD54UR_HfHmu3Z1iYw@mail.gmail.com> (raw)
In-Reply-To: <20210604005036.4187184-1-ira.weiny@intel.com>
On Thu, Jun 3, 2021 at 5:51 PM <ira.weiny@intel.com> wrote:
>
> From: Ira Weiny <ira.weiny@intel.com>
>
> The information required to map registers based on capabilities is
> contained within the bars themselves. This means the bar must be mapped
> to read the information needed and then unmapped to map the individual
> parts of the BAR based on capabilities.
>
> Change cxl_setup_device_regs() to return a new cxl_register_map, change
> the name to cxl_probe_device_regs(). Allocate and place
> cxl_register_maps on a list while processing all of the specified
> register blocks.
>
> After probing all the register blocks go back and map smaller registers
> blocks based on their capabilities and dispose of the cxl_register_maps.
>
> NOTE: pci_iomap() is not managed automatically via pcim_enable_device()
> so be careful to call pci_iounmap() correctly.
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> Link: https://lore.kernel.org/r/20210528004922.3980613-4-ira.weiny@intel.com
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
>
> ---
> Changes for V3.1
> Fix 0-day
>
> >> drivers/cxl/core.c:40:17: warning: variable 'register_block' set but not used [-Wunused-but-set-variable]
> 40 | void __iomem *register_block;
Just a note for next time if you want to be friendly to "b4 am" using
maintainers. Roll the version and include the patch number in the
resend, i.e.: in this case: "[PATCH v4 3/5] cxl/mem: Map registers
based on capabilities". I was able to manually create a bundle in the
proper order on patchwork for the two "3.1" updates.
next prev parent reply other threads:[~2021-06-06 0:30 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-28 0:49 [PATCH V3 0/5] Map register blocks individually ira.weiny
2021-05-28 0:49 ` [PATCH V3 1/5] cxl/mem: Introduce cxl_decode_register_block() ira.weiny
2021-05-28 0:49 ` [PATCH V3 2/5] cxl/mem: Reserve all device regions at once ira.weiny
2021-05-28 0:49 ` [PATCH V3 3/5] cxl/mem: Map registers based on capabilities ira.weiny
2021-06-04 0:50 ` [PATCH V3.1] " ira.weiny
2021-06-06 0:30 ` Dan Williams [this message]
2021-05-28 0:49 ` [PATCH V3 4/5] cxl/mem: Reserve individual register block regions ira.weiny
2021-06-04 0:53 ` [PATCH V3.1] " ira.weiny
2021-05-28 0:49 ` [PATCH V3 5/5] cxl/pci: Add HDM decoder capabilities ira.weiny
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