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From: "Huang, Ray" <Ray.Huang@amd.com>
To: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: "Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
	Viresh Kumar <viresh.kumar@linaro.org>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Borislav Petkov <bp@suse.de>,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@kernel.org>,
	Linux PM <linux-pm@vger.kernel.org>,
	"Sharma, Deepak" <Deepak.Sharma@amd.com>,
	"Deucher, Alexander" <Alexander.Deucher@amd.com>,
	"Limonciello, Mario" <Mario.Limonciello@amd.com>,
	"Fontenot, Nathan" <Nathan.Fontenot@amd.com>,
	"Su, Jinzhou (Joe)" <Jinzhou.Su@amd.com>,
	"Du, Xiaojian" <Xiaojian.Du@amd.com>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	the arch/x86 maintainers <x86@kernel.org>
Subject: RE: [PATCH v2 04/21] ACPI: CPPC: add cppc enable register function
Date: Wed, 20 Oct 2021 11:13:50 +0000	[thread overview]
Message-ID: <CY4PR1201MB0246A7ECA4E8143CC6E4933DECBE9@CY4PR1201MB0246.namprd12.prod.outlook.com> (raw)
In-Reply-To: <CAJZ5v0g58vrHNcOEoWUCKmTxraSTuCzVLffzEAgz7TPa8+TNyw@mail.gmail.com>

[AMD Official Use Only]

> -----Original Message-----
> From: Rafael J. Wysocki <rafael@kernel.org>
> Sent: Wednesday, October 20, 2021 1:00 AM
> To: Huang, Ray <Ray.Huang@amd.com>
> Cc: Rafael J . Wysocki <rafael.j.wysocki@intel.com>; Viresh Kumar
> <viresh.kumar@linaro.org>; Shuah Khan <skhan@linuxfoundation.org>;
> Borislav Petkov <bp@suse.de>; Peter Zijlstra <peterz@infradead.org>; Ingo
> Molnar <mingo@kernel.org>; Linux PM <linux-pm@vger.kernel.org>;
> Sharma, Deepak <Deepak.Sharma@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Limonciello, Mario
> <Mario.Limonciello@amd.com>; Fontenot, Nathan
> <Nathan.Fontenot@amd.com>; Su, Jinzhou (Joe) <Jinzhou.Su@amd.com>;
> Du, Xiaojian <Xiaojian.Du@amd.com>; Linux Kernel Mailing List <linux-
> kernel@vger.kernel.org>; the arch/x86 maintainers <x86@kernel.org>
> Subject: Re: [PATCH v2 04/21] ACPI: CPPC: add cppc enable register function
> 
> On Sun, Sep 26, 2021 at 11:06 AM Huang Rui <ray.huang@amd.com> wrote:
> >
> > From: Jinzhou Su <Jinzhou.Su@amd.com>
> >
> > Add a new function to enable CPPC feature. This function will write
> > Continuous Performance Control package EnableRegister field on the
> > processor.
> 
> And what is going to take place after this write?
> 
> Also, it would be good to mention that the user of this function will be added
> subsequently.

After the enable flag is set, the processor hardware can accept the performance goals such as desired perf that programed by kernel and control the processor frequency according to the performance value.
I will mention this in the comment in V3.

> 
> > Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> >  drivers/acpi/cppc_acpi.c | 48
> > ++++++++++++++++++++++++++++++++++++++++
> >  include/acpi/cppc_acpi.h |  5 +++++
> >  2 files changed, 53 insertions(+)
> >
> > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index
> > 2efe2ba97d96..b285960c35e7 100644
> > --- a/drivers/acpi/cppc_acpi.c
> > +++ b/drivers/acpi/cppc_acpi.c
> > @@ -1220,6 +1220,54 @@ int cppc_get_perf_ctrs(int cpunum, struct
> > cppc_perf_fb_ctrs *perf_fb_ctrs)  }
> > EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
> >
> > +/**
> > + * cppc_set_enable - Set to enable CPPC on the processor by writing
> > +the
> > + * Continuous Performance Control package EnableRegister feild.
> > + * @cpu: CPU for which to enable CPPC register.
> > + * @enable: 0 - disable, 1 - enable CPPC feature on the processor.
> > + *
> > + * Return: 0 for success, -ERRNO or -EIO otherwise.
> > + */
> > +int cppc_set_enable(int cpu, u32 enable) {
> > +       int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > +       struct cpc_register_resource *enable_reg;
> > +       struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> > +       struct cppc_pcc_data *pcc_ss_data = NULL;
> > +       int ret = -1;
> > +
> > +       /* check the input value*/
> > +       if (cpu < 0 || cpu > num_possible_cpus() - 1 || enable > 1)
> 
> Why not use cpu_possible()?  And why enable > 1 is a problem?
> 

Yes, you're right, cpu_possible() is better here.
Will remove "enable > 1", and yes, we should support "disable" as well.


> > +               return -ENODEV;
> 
> -EINVAL
> 

Updated.

> > +
> > +       if (!cpc_desc) {
> 
> if this is checked, the cpu_possible() check above is redundant.

Hmm, if acpi_cppc_processor_probe got failed, some one outside acpi driver would like to call this helper.
Is that possible we get a null cpc descriptor here? Or anything I missed.

> 
> > +               pr_debug("No CPC descriptor for CPU:%d\n", cpu);
> > +               return -ENODEV;
> > +       }
> > +
> > +       enable_reg = &cpc_desc->cpc_regs[ENABLE];
> > +
> > +       if (CPC_IN_PCC(enable_reg)) {
> > +
> > +               if (pcc_ss_id < 0)
> > +                       return -EIO;
> > +
> > +               ret = cpc_write(cpu, enable_reg, enable);
> > +               if (ret)
> > +                       return ret;
> > +
> > +               pcc_ss_data = pcc_data[pcc_ss_id];
> > +
> > +               down_write(&pcc_ss_data->pcc_lock);
> > +               /* after writing CPC, transfer the ownership of PCC to platfrom */
> > +               ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> > +               up_write(&pcc_ss_data->pcc_lock);
> > +       }
> 
> Does it really need to do nothing if the register is not in PCC?  If so, then why?
> 

Hmm, do you mean we should take care the cases for enabling behavior if register in other spaces such as SYSTEM_MEMORY or FIXED_HARDWARE on different kinds of SBIOS implementation?

Thanks,
Ray

  reply	other threads:[~2021-10-20 11:14 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-26  9:05 [PATCH v2 00/21] cpufreq: introduce a new AMD CPU frequency control mechanism Huang Rui
2021-09-26  9:05 ` [PATCH v2 01/21] x86/cpufreatures: add AMD Collaborative Processor Performance Control feature flag Huang Rui
2021-09-26  9:05 ` [PATCH v2 02/21] x86/msr: add AMD CPPC MSR definitions Huang Rui
2021-09-26  9:05 ` [PATCH v2 03/21] ACPI: CPPC: Check online CPUs for determining _CPC is valid Huang Rui
2021-10-19 16:52   ` Rafael J. Wysocki
2021-10-20 11:15     ` Huang, Ray
2021-09-26  9:05 ` [PATCH v2 04/21] ACPI: CPPC: add cppc enable register function Huang Rui
2021-09-28 17:06   ` Fontenot, Nathan
2021-10-13 12:28     ` Huang, Ray
2021-10-19 16:59   ` Rafael J. Wysocki
2021-10-20 11:13     ` Huang, Ray [this message]
2021-10-20 13:32       ` Rafael J. Wysocki
2021-10-21  3:41         ` Huang, Ray
2021-09-26  9:05 ` [PATCH v2 05/21] cpufreq: amd: introduce a new amd pstate driver to support future processors Huang Rui
2021-09-28 20:40   ` Fontenot, Nathan
2021-10-14 10:14     ` Huang, Ray
2021-09-26  9:05 ` [PATCH v2 06/21] cpufreq: amd: add fast switch function for amd-pstate module Huang Rui
2021-09-26  9:05 ` [PATCH v2 07/21] cpufreq: amd: add acpi cppc function as the backend for legacy processors Huang Rui
2021-09-26  9:05 ` [PATCH v2 08/21] cpufreq: amd: add trace for amd-pstate module Huang Rui
2021-10-06  8:12   ` Giovanni Gherdovich
2021-10-21 10:19     ` Huang, Ray
2021-09-26  9:05 ` [PATCH v2 09/21] cpufreq: amd: add boost mode support for amd-pstate Huang Rui
2021-09-26  9:05 ` [PATCH v2 10/21] cpufreq: amd: add amd-pstate checking support check attribute Huang Rui
2021-09-28 21:24   ` Fontenot, Nathan
2021-10-14 10:26     ` Huang, Ray
2021-09-26  9:05 ` [PATCH v2 11/21] cpufreq: amd: add amd-pstate frequencies attributes Huang Rui
2021-09-28 21:35   ` Fontenot, Nathan
2021-10-14 10:35     ` Huang, Ray
2021-09-26  9:05 ` [PATCH v2 12/21] cpufreq: amd: add amd-pstate performance attributes Huang Rui
2021-09-26  9:05 ` [PATCH v2 13/21] cpupower: add AMD P-state capability flag Huang Rui
2021-09-26  9:05 ` [PATCH v2 14/21] cpupower: add the function to check amd-pstate enabled Huang Rui
2021-09-26  9:05 ` [PATCH v2 15/21] cpupower: initial AMD P-state capability Huang Rui
2021-09-26  9:06 ` [PATCH v2 16/21] cpupower: add the function to get the sysfs value from specific table Huang Rui
2021-09-26  9:06 ` [PATCH v2 17/21] cpupower: add amd-pstate sysfs definition and access helper Huang Rui
2021-09-26  9:06 ` [PATCH v2 18/21] cpupower: enable boost state support for amd-pstate module Huang Rui
2021-09-26  9:06 ` [PATCH v2 19/21] cpupower: move print_speed function into misc helper Huang Rui
2021-09-26  9:06 ` [PATCH v2 20/21] cpupower: print amd-pstate information on cpupower Huang Rui
2021-09-26  9:06 ` [PATCH v2 21/21] Documentation: amd-pstate: add amd-pstate driver introduction Huang Rui
2021-10-13 16:23   ` Giovanni Gherdovich
2021-10-14 11:30     ` Huang, Ray

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