AW: [PATCH] gpu: ipu-v3: Fix dev_dbg frequency output

["Jonas Mark (BT-FIR/ENG1-Grb)" <Mark.Jonas@de.bosch.com>]

Hi,

> From: Leo Ruan <tingquan.ruan@cn.bosch.com>
> 
> This commit corrects the printing of the IPU clock error percentage if it is
> between -0.1% to -0.9%. For example, if the pixel clock requested is 27.2
> MHz but only 27.0 MHz can be achieved the deviation is -0.8%.
> But the fixed point math had a flaw and calculated error of 0.2%.
> 
> Before:
>   Clocks: IPU 270000000Hz DI 24716667Hz Needed 27200000Hz
>   IPU clock can give 27000000 with divider 10, error 0.2%
>   Want 27200000Hz IPU 270000000Hz DI 24716667Hz using IPU,
> 27000000Hz
> 
> After:
>   Clocks: IPU 270000000Hz DI 24716667Hz Needed 27200000Hz
>   IPU clock can give 27000000 with divider 10, error -0.8%
>   Want 27200000Hz IPU 270000000Hz DI 24716667Hz using IPU,
> 27000000Hz
> 
> Signed-off-by: Leo Ruan <tingquan.ruan@cn.bosch.com>
> Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
> ---
>  drivers/gpu/ipu-v3/ipu-di.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c index
> b4a31d506fcc..74eca68891ad 100644
> --- a/drivers/gpu/ipu-v3/ipu-di.c
> +++ b/drivers/gpu/ipu-v3/ipu-di.c
> @@ -451,8 +451,9 @@ static void ipu_di_config_clock(struct ipu_di *di,
> 
>  		error = rate / (sig->mode.pixelclock / 1000);
> 
> -		dev_dbg(di->ipu->dev, "  IPU clock can give %lu with divider
> %u, error %d.%u%%\n",
> -			rate, div, (signed)(error - 1000) / 10, error % 10);
> +		dev_dbg(di->ipu->dev, "  IPU clock can give %lu with divider
> %u, error %c%d.%d%%\n",
> +			rate, div, error < 1000 ? '-' : '+',
> +			abs(error - 1000) / 10, abs(error - 1000) % 10);
> 
>  		/* Allow a 1% error */
>  		if (error < 1010 && error >= 990) {

Is there anything I can do to help getting this patch mainline?

Cheers,
Mark

Mark Jonas 

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