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From: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
To: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
	"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bp@alien8.de" <bp@alien8.de>
Subject: RE: [PATCH v3 1/6] EDAC/amd64: Add Family 17h Model 30h PCI IDs
Date: Thu, 21 Mar 2019 20:30:02 +0000	[thread overview]
Message-ID: <SN6PR12MB2639CDDA70C504DFEF5EE7B8F8420@SN6PR12MB2639.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20190228153558.127292-1-Yazen.Ghannam@amd.com>

Hi Boris,

Any comments on this set?

Thanks,
Yazen

> -----Original Message-----
> From: linux-edac-owner@vger.kernel.org <linux-edac-owner@vger.kernel.org> On Behalf Of Ghannam, Yazen
> Sent: Thursday, February 28, 2019 9:36 AM
> To: linux-edac@vger.kernel.org
> Cc: Ghannam, Yazen <Yazen.Ghannam@amd.com>; linux-kernel@vger.kernel.org; bp@alien8.de
> Subject: [PATCH v3 1/6] EDAC/amd64: Add Family 17h Model 30h PCI IDs
> 
> From: Yazen Ghannam <yazen.ghannam@amd.com>
> 
> Add the new Family 17h Model 30h PCI IDs to the AMD64 EDAC module.
> 
> This also fixes a probe failure that appeared when some other PCI IDs
> for Family 17h Model 30h were added to the AMD NB code.
> 
> Fixes: be3518a16ef2 (x86/amd_nb: Add PCI device IDs for family 17h, model 30h)
> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
> ---
> Link:
> https://lkml.kernel.org/r/20190226172532.12924-1-Yazen.Ghannam@amd.com
> 
> v2->v3:
> * No change.
> 
> v1->v2:
> * Write out "Family" and "Model" in commit message.
> * Sort model checks in increasing order.
> 
>  drivers/edac/amd64_edac.c | 13 +++++++++++++
>  drivers/edac/amd64_edac.h |  3 +++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
> index 6ea98575a402..98e8da9d9f5b 100644
> --- a/drivers/edac/amd64_edac.c
> +++ b/drivers/edac/amd64_edac.c
> @@ -2211,6 +2211,15 @@ static struct amd64_family_type family_types[] = {
>  			.dbam_to_cs		= f17_base_addr_to_cs_size,
>  		}
>  	},
> +	[F17_M30H_CPUS] = {
> +		.ctl_name = "F17h_M30h",
> +		.f0_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F0,
> +		.f6_id = PCI_DEVICE_ID_AMD_17H_M30H_DF_F6,
> +		.ops = {
> +			.early_channel_count	= f17_early_channel_count,
> +			.dbam_to_cs		= f17_base_addr_to_cs_size,
> +		}
> +	},
>  };
> 
>  /*
> @@ -3203,6 +3212,10 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
>  			fam_type = &family_types[F17_M10H_CPUS];
>  			pvt->ops = &family_types[F17_M10H_CPUS].ops;
>  			break;
> +		} else if (pvt->model >= 0x30 && pvt->model <= 0x3f) {
> +			fam_type = &family_types[F17_M30H_CPUS];
> +			pvt->ops = &family_types[F17_M30H_CPUS].ops;
> +			break;
>  		}
>  		/* fall through */
>  	case 0x18:
> diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
> index 4242f8e39c18..de8dbb0b42b5 100644
> --- a/drivers/edac/amd64_edac.h
> +++ b/drivers/edac/amd64_edac.h
> @@ -117,6 +117,8 @@
>  #define PCI_DEVICE_ID_AMD_17H_DF_F6	0x1466
>  #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
>  #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
> +#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
> +#define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496
> 
>  /*
>   * Function 1 - Address Map
> @@ -284,6 +286,7 @@ enum amd_families {
>  	F16_M30H_CPUS,
>  	F17_CPUS,
>  	F17_M10H_CPUS,
> +	F17_M30H_CPUS,
>  	NUM_FAMILIES,
>  };
> 
> --
> 2.17.1


  parent reply	other threads:[~2019-03-21 20:30 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-28 15:36 [PATCH v3 1/6] EDAC/amd64: Add Family 17h Model 30h PCI IDs Ghannam, Yazen
2019-02-28 15:36 ` [PATCH v3 3/6] EDAC/amd64: Support more than two Unified Memory Controllers Ghannam, Yazen
2019-03-23 12:15   ` Borislav Petkov
2019-03-23 17:22     ` Ghannam, Yazen
2019-02-28 15:36 ` [PATCH v3 2/6] EDAC/amd64: Use a macro for iterating over " Ghannam, Yazen
2019-02-28 15:36 ` [PATCH v3 5/6] EDAC/amd64: Support more than two Controllers for Chip Select handling Ghannam, Yazen
2019-02-28 15:36 ` [PATCH v3 4/6] EDAC/amd64: Recognize x16 Symbol Size Ghannam, Yazen
2019-02-28 15:36 ` [PATCH v3 6/6] EDAC/amd64: Adjust printed Chip Select sizes when interleaved Ghannam, Yazen
2019-03-21 20:30 ` Ghannam, Yazen [this message]
2019-03-22 16:33   ` [PATCH v3 1/6] EDAC/amd64: Add Family 17h Model 30h PCI IDs Kim Phillips
2019-03-22 16:46     ` Borislav Petkov

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