From: Borislav Petkov <bp@alien8.de>
To: Yazen Ghannam <yazen.ghannam@amd.com>
Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
mchehab@kernel.org, tony.luck@intel.com, james.morse@arm.com,
rric@kernel.org, Smita.KoralahalliChannabasappa@amd.com,
william.roche@oracle.com
Subject: Re: [PATCH 4/4] EDAC/amd64: Add DDR5 support and related register changes
Date: Tue, 14 Dec 2021 17:22:20 +0100 [thread overview]
Message-ID: <YbjEvMTaW9+AiBZ8@zn.tnic> (raw)
In-Reply-To: <YbeHD5PW0sv4O13r@yaz-ubuntu>
On Mon, Dec 13, 2021 at 05:46:55PM +0000, Yazen Ghannam wrote:
> Yeah, sorry it's not clear. The purpose of the flag is to indicate some minor
> changes that show up with future systems like register offsets changes, etc. I
> didn't want to tie the name to a specific model or core name. I went with DDR5
> as a new feature that shows up with these changes, but they're not directly
> tied to DDR5.
>
> But yes, a system may support DDR5 and DDR4. And this can be detected from the
> hardware.
>
> What do you think about calling the flag "uses_f19h_m10h_offsets" or something
> like that? I was trying to avoid family/model in the name, but the code
> already does this all over. And the convention has been to call something by
> the first family/model where it shows up.
Good question.
So AFAIU, these register offset changes are probably going to propagate
beyond F19M10... In any case, they won't be tied to the family/model
so your flag idea is in the right direction, AFAICT. I'd do something
shorter, though, so that the code accessing it is short'n'sweet:
if (pvt->flags.f19h_regs_ng) - "new generation" regs :-)
or even
if (pvt->flags.zn_new_regs_fmt)
or whatever that's called. The GPU UMC is called UMC_v2 so I guess
if (pvt->flags.zn_regs_v2)
:-)
You get the idea...
With an ample explanation in a comment what that means, ofc.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2021-12-14 16:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-08 17:43 [PATCH 0/4] AMD Family 19h Models 10h-1Fh Updates Yazen Ghannam
2021-12-08 17:43 ` [PATCH 1/4] EDAC: Add RDDR5 and LRDDR5 memory types Yazen Ghannam
2021-12-08 17:43 ` [PATCH 2/4] EDAC/amd64: Add support for AMD Family 19h Models 10h-1Fh and A0h-AFh Yazen Ghannam
2021-12-08 17:43 ` [PATCH 3/4] EDAC/amd64: Check register values from all UMCs Yazen Ghannam
2021-12-10 12:34 ` Borislav Petkov
2021-12-13 17:24 ` Yazen Ghannam
2021-12-08 17:43 ` [PATCH 4/4] EDAC/amd64: Add DDR5 support and related register changes Yazen Ghannam
2021-12-10 12:41 ` Borislav Petkov
2021-12-13 17:46 ` Yazen Ghannam
2021-12-14 16:22 ` Borislav Petkov [this message]
2021-12-10 12:44 ` [PATCH 0/4] AMD Family 19h Models 10h-1Fh Updates Borislav Petkov
2021-12-13 17:23 ` Yazen Ghannam
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