From: Peter Zijlstra <peterz@infradead.org>
To: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>,
Andy Lutomirski <luto@kernel.org>,
x86@kernel.org, Kostya Serebryany <kcc@google.com>,
Andrey Ryabinin <ryabinin.a.a@gmail.com>,
Andrey Konovalov <andreyknvl@gmail.com>,
Alexander Potapenko <glider@google.com>,
Taras Madan <tarasmadan@google.com>,
Dmitry Vyukov <dvyukov@google.com>,
"H . J . Lu" <hjl.tools@gmail.com>,
Andi Kleen <ak@linux.intel.com>,
Rick Edgecombe <rick.p.edgecombe@intel.com>,
linux-mm@kvack.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCHv6 04/11] x86/mm: Handle LAM on context switch
Date: Mon, 15 Aug 2022 15:42:25 +0200 [thread overview]
Message-ID: <YvpNQSEtu+Tbqrpd@worktop.programming.kicks-ass.net> (raw)
In-Reply-To: <20220815041803.17954-5-kirill.shutemov@linux.intel.com>
On Mon, Aug 15, 2022 at 07:17:56AM +0300, Kirill A. Shutemov wrote:
> diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
> index c1e31e9a85d7..fdc0b69b5da7 100644
> --- a/arch/x86/mm/tlb.c
> +++ b/arch/x86/mm/tlb.c
> @@ -154,17 +154,18 @@ static inline u16 user_pcid(u16 asid)
> return ret;
> }
>
> -static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
> +static inline unsigned long build_cr3(pgd_t *pgd, u16 asid, unsigned long lam)
> {
> if (static_cpu_has(X86_FEATURE_PCID)) {
> - return __sme_pa(pgd) | kern_pcid(asid);
> + return __sme_pa(pgd) | kern_pcid(asid) | lam;
> } else {
> VM_WARN_ON_ONCE(asid != 0);
> - return __sme_pa(pgd);
> + return __sme_pa(pgd) | lam;
> }
> }
>
> -static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
> +static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid,
> + unsigned long lam)
> {
> VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
> /*
> @@ -173,7 +174,7 @@ static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
> * boot because all CPU's the have same capabilities:
> */
> VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
> - return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
> + return __sme_pa(pgd) | kern_pcid(asid) | lam | CR3_NOFLUSH;
> }
Looking at this; I wonder if we want something like this:
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -157,6 +157,7 @@ static inline u16 user_pcid(u16 asid)
static inline unsigned long build_cr3(pgd_t *pgd, u16 asid, unsigned long lam)
{
if (static_cpu_has(X86_FEATURE_PCID)) {
+ VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
return __sme_pa(pgd) | kern_pcid(asid) | lam;
} else {
VM_WARN_ON_ONCE(asid != 0);
@@ -167,14 +168,13 @@ static inline unsigned long build_cr3(pg
static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid,
unsigned long lam)
{
- VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
/*
* Use boot_cpu_has() instead of this_cpu_has() as this function
* might be called during early boot. This should work even after
* boot because all CPU's the have same capabilities:
*/
VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
- return __sme_pa(pgd) | kern_pcid(asid) | lam | CR3_NOFLUSH;
+ return build_cr3(pgd, asid, lam) | CR3_NOFLUSH;
}
/*
next prev parent reply other threads:[~2022-08-15 13:42 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-15 4:17 [PATCHv6 00/11] Linear Address Masking enabling Kirill A. Shutemov
2022-08-15 4:17 ` [PATCHv6 01/11] x86/mm: Fix CR3_ADDR_MASK Kirill A. Shutemov
2022-08-15 4:17 ` [PATCHv6 02/11] x86: CPUID and CR3/CR4 flags for Linear Address Masking Kirill A. Shutemov
2022-08-15 4:17 ` [PATCHv6 03/11] mm: Pass down mm_struct to untagged_addr() Kirill A. Shutemov
2022-08-15 4:17 ` [PATCHv6 04/11] x86/mm: Handle LAM on context switch Kirill A. Shutemov
2022-08-15 13:33 ` Peter Zijlstra
2022-08-15 13:42 ` Peter Zijlstra [this message]
2022-08-15 17:37 ` Kirill A. Shutemov
2022-08-15 18:02 ` Peter Zijlstra
2022-08-16 0:07 ` [PATCHv6.1 " Kirill A. Shutemov
2022-08-15 4:17 ` [PATCHv6 05/11] x86/uaccess: Provide untagged_addr() and remove tags before address check Kirill A. Shutemov
2022-08-15 4:17 ` [PATCHv6 06/11] x86/mm: Provide arch_prctl() interface for LAM Kirill A. Shutemov
2022-08-15 13:37 ` Peter Zijlstra
2022-08-15 17:52 ` Kirill A. Shutemov
2022-08-16 0:10 ` [PATCHv6.1 " Kirill A. Shutemov
2022-08-22 9:32 ` [PATCHv6 " Alexander Potapenko
2022-08-23 13:16 ` Alexander Potapenko
2022-08-15 4:17 ` [PATCHv6 07/11] x86: Expose untagging mask in /proc/$PID/arch_status Kirill A. Shutemov
2022-08-15 4:18 ` [PATCHv6 08/11] selftests/x86/lam: Add malloc and tag-bits test cases for linear-address masking Kirill A. Shutemov
2022-08-19 5:17 ` Hu, Robert
2022-08-22 5:21 ` Zhang, Weihong
2022-08-15 4:18 ` [PATCHv6 09/11] selftests/x86/lam: Add mmap and SYSCALL " Kirill A. Shutemov
2022-08-19 8:15 ` Hu, Robert
2022-08-22 8:47 ` Zhang, Weihong
2022-08-15 4:18 ` [PATCHv6 10/11] selftests/x86/lam: Add io_uring " Kirill A. Shutemov
2022-08-15 4:18 ` [PATCHv6 11/11] selftests/x86/lam: Add inherit " Kirill A. Shutemov
2022-08-15 13:43 ` [PATCHv6 00/11] Linear Address Masking enabling Peter Zijlstra
2022-08-23 8:58 ` Alexander Potapenko
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