From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, Mark Rutland <mark.rutland@arm.com>,
kernel-team@android.com,
Anshuman Khandual <anshuman.khandual@arm.com>,
Marc Zyngier <maz@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-kernel@vger.kernel.org,
Doug Anderson <dianders@chromium.org>,
Catalin Marinas <catalin.marinas@arm.com>
Subject: Re: [PATCH 0/8] Relax sanity checking for mismatched AArch32 EL1
Date: Thu, 16 Apr 2020 14:09:30 +0530 [thread overview]
Message-ID: <a86108a91975cacf94adc2a2101fba1b@codeaurora.org> (raw)
In-Reply-To: <20200414213114.2378-1-will@kernel.org>
On 2020-04-15 03:01, Will Deacon wrote:
> Hi all,
>
> For better or worse, there are SoCs in production where some, but not
> all of the CPUs, support AArch32 at EL1 and above. Right now, that
> results in "SANITY CHECK" warnings during boot and an unconditional
> kernel taint.
>
> This patch series tries to do a bit better: the only time we care about
> AArch32 at EL1 is for KVM, so rather than throw our toys out of the
> pram, we can instead just disable support for 32-bit guests on these
> systems. In the unlikely scenario of a late CPU hotplug being the first
> time we notice that AArch32 is not available, then we fail the hotplug
> (right now we let the thing come online, which leads to hilarious
> results for any pre-existing 32-bit guests).
>
> Feedback welcome,
>
> Will
>
Thanks Will, tested this series on QCOM SC7180 and SM8150 SoCs.
For the entire series,
Tested-by: saiprakash.ranjan@codeaurora.org
-Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2020-04-16 8:45 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-14 21:31 [PATCH 0/8] Relax sanity checking for mismatched AArch32 EL1 Will Deacon
2020-04-14 21:31 ` [PATCH 1/8] arm64: cpufeature: Relax check for IESB support Will Deacon
2020-04-15 10:02 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 2/8] arm64: cpufeature: Spell out register fields for ID_ISAR4 and ID_PFR1 Will Deacon
2020-04-15 10:09 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 3/8] arm64: cpufeature: Add CPU capability for AArch32 EL1 support Will Deacon
2020-04-15 8:55 ` Marc Zyngier
2020-04-15 17:00 ` Will Deacon
2020-04-15 10:13 ` Suzuki K Poulose
2020-04-15 10:14 ` Will Deacon
2020-04-15 13:15 ` Suzuki K Poulose
2020-04-15 13:22 ` Marc Zyngier
2020-04-17 9:44 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 4/8] arm64: cpufeature: Remove redundant call to id_aa64pfr0_32bit_el0() Will Deacon
2020-04-15 10:25 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 5/8] arm64: cpufeature: Factor out checking of AArch32 features Will Deacon
2020-04-15 10:36 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 6/8] arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit only Will Deacon
2020-04-15 10:43 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 7/8] arm64: cpufeature: Relax checks for AArch32 support at EL[0-2] Will Deacon
2020-04-15 10:50 ` Suzuki K Poulose
2020-04-15 10:58 ` Will Deacon
2020-04-15 11:37 ` Suzuki K Poulose
2020-04-15 12:29 ` Will Deacon
2020-04-17 9:37 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 8/8] arm64: cpufeature: Add an overview comment for the cpufeature framework Will Deacon
2020-04-16 11:58 ` Will Deacon
2020-04-16 14:59 ` Suzuki K Poulose
2020-04-16 15:26 ` Marc Zyngier
2020-04-16 18:12 ` Will Deacon
2020-04-16 8:39 ` Sai Prakash Ranjan [this message]
2020-04-16 10:26 ` [PATCH 0/8] Relax sanity checking for mismatched AArch32 EL1 Sai Prakash Ranjan
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