Re: setup_boot_APIC_clock() NULL dereference during early boot on reduced hardware platforms

From: Thomas Gleixner <tglx@linutronix.de>
To: "Li, Aubrey" <aubrey.li@linux.intel.com>
Cc: Aubrey Li <aubrey.intel@gmail.com>,
	Daniel Drake <drake@endlessm.com>,
	x86@kernel.org, Ingo Molnar <mingo@redhat.com>,
	"H . Peter Anvin" <hpa@zytor.com>,
	Linux Kernel <linux-kernel@vger.kernel.org>,
	Endless Linux Upstreaming Team <linux@endlessm.com>,
	Tom Lendacky <thomas.lendacky@amd.com>
Subject: Re: setup_boot_APIC_clock() NULL dereference during early boot on reduced hardware platforms
Date: Thu, 1 Aug 2019 12:13:16 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.21.1908011054210.1965@nanos.tec.linutronix.de> (raw)
In-Reply-To: <81666b28-d029-56c3-8978-90abc219d1b7@linux.intel.com>

On Thu, 1 Aug 2019, Li, Aubrey wrote:
> On 2019/8/1 16:13, Thomas Gleixner wrote:
> > The point is that it does not matter which vendor a CPU comes from. The
> > kernel does support legacyless boot when the frequencies are known. Whether
> > that's currently possible on that particular CPU is a different question.
> > 
> Yeah, I should specify, Daniel, your platform needs a global clock event, ;-)

Care to look at the manuals before making assumptions?

  2.1.9 Timers

   Each core includes the following timers. These timers do not vary in
   frequency regardless of the current P-state or C-state.

   * Core::X86::Msr::TSC; the TSC increments at the rate specified by the
     P0 Pstate. See Core::X86::Msr::PStateDef.

   * The APIC timer (Core::X86::Apic::TimerInitialCount and
     Core::X86::Apic::TimerCurrentCount), which increments at the rate of
     2xCLKIN; the APIC timer may increment in units of between 1 and 8.

The Ryzens use a 100MHz input clock for the APIC normally, but I'm not sure
whether this is subject to overclocking. If so then it should be possible
to figure that out somehow. Tom?

Thanks,

	tglx