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[108.223.40.66]) by smtp.gmail.com with ESMTPSA id 143-v6sm5567147pfy.156.2018.08.17.17.44.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Aug 2018 17:44:10 -0700 (PDT) Subject: Re: Crash in MM code in v4.4.y, v4.9.y with TRANSPARENT_HUGEPAGE enabled To: Linus Torvalds Cc: Linux Kernel Mailing List , Greg Kroah-Hartman , Andi Kleen , Thomas Gleixner , Josh Poimboeuf , Dave Hansen , David Woodhouse , the arch/x86 maintainers , Dmitry Vyukov , Hugh Dickins , "Kirill A. Shutemov" , Andrea Arcangeli References: <20180817222733.GA18575@roeck-us.net> From: Guenter Roeck Message-ID: Date: Fri, 17 Aug 2018 17:44:08 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/17/2018 05:25 PM, Linus Torvalds wrote: > On Fri, Aug 17, 2018 at 3:27 PM Guenter Roeck wrote: >> >> [ 6.649970] random: crng init done >> [ 6.689002] BUG: unable to handle kernel paging request at ffffeafffa1a0020 > > Hmm. Lots of bits set. > >> [ 6.689082] RIP: 0010:[] [] page_remove_rmap+0x10/0x230 >> [ 6.689082] RSP: 0018:ffffc900007abc18 EFLAGS: 00000296 >> [ 6.689082] RAX: ffffea0005e58000 RBX: ffffeafffa1a0000 RCX: 0000000020200000 >> [ 6.689082] RDX: 00003fffffe00000 RSI: 0000000000000001 RDI: ffffeafffa1a0000 > > Is that RDX value the same value as PHYSICAL_PMD_PAGE_MASK? > > If I did my math right, it would be, if your CPU has 46 bits of > physical memory. Might that be the case? > Yes. > The reason I mention that is because we had the bug with spurious > inversion of the zero pte/pmd, fixed by > > f19f5c49bbc3 ("x86/speculation/l1tf: Exempt zeroed PTEs from inversion") > I applied that patch, but it didn't help. I get exactly the same crash and traceback. > and that would make a zeroed pmd entry be inverted by > PHYSICAL_PMD_PAGE_MASK, and then you get odd garbage page pointers > etc. > > Maybe. I could have gotten the math wrong too, but it sounds like the > register contents _potentially_ might match up with something like > this, and then we'd zap a bogus hugepage because of some confusion. > > Although then I'd have expected the bisection to hit > "x86/speculation/l1tf: Invert all not present mappings" instead of the > one you hit, so I don't know. > > Plus I'd have expected the problem to have been in mainline too, and > apparently it's just the 4.4 and 4.9 backports. > Personally I suspect that something went wrong or is missing in the backport from 4.14 to 4.9. 5-level paging was introduced in between, and thp support was extended to support additional architectures. With all those changes, it is easy to miss something. Only I have no idea what that might be. Guenter