From: "Andy Lutomirski" <luto@kernel.org>
To: "Dave Hansen" <dave.hansen@intel.com>,
"Ingo Molnar" <mingo@kernel.org>,
"Ira Weiny" <ira.weiny@intel.com>
Cc: "Borislav Petkov" <bp@alien8.de>,
"Rik van Riel" <riel@surriel.com>,
"the arch/x86 maintainers" <x86@kernel.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
kernel-team@fb.com
Subject: Re: [RFC PATCH 5/5] x86/entry: Store CPU info on exception entry
Date: Tue, 09 Aug 2022 14:19:19 -0700 [thread overview]
Message-ID: <c2f42cfd-82d4-4ab7-92b9-a173d6cdd29d@www.fastmail.com> (raw)
In-Reply-To: <01768c70-a012-0d08-cfa5-a7a87ff0a19c@intel.com>
On Mon, Aug 8, 2022, at 9:16 AM, Dave Hansen wrote:
> On 8/8/22 04:03, Ingo Molnar wrote:
>>> Again, I don't believe this is too much overhead but I don't want people
>>> to say it was not discussed.
>> Is it necessary to do this, what are the alternatives, can this overhead be
>> avoided?
>
> One thing Andy mentioned is that we _could_ get it down to two instructions:
>
> rdgsbase $reg
> push $reg
>
> This could be hidden in:
>
> PUSH_PTREGS_AUXILIARY
>
> where, today, it would only net add a single instruction. But, if we
> ever add more stuff to PUSH_PTREGS_AUXILIARY, it would move back to
> needing two instructions since we'd need both the:
>
> subq $PTREGS_AUX_SIZE, %rsp
>
> and something to write gsbase to the stack.
>
> That doesn't get us the smp_processor_id() directly, but we can derive
> it later on from the gsbase value.
>
> The downside is that we're doing it in assembly. We'd also have
> something additional which is a bit uglier and that reads memory on
> !X86_FEATURE_FSGSBASE, probably:
>
> movq PER_CPU_VAR(cpu_number), %reg
> push %reg
Nah, I believe the same value that RDGSBASE reads is already in percpu memory as 'per_cpu_offset', so the alternative can just read that and the code that uses it doesn’t need to care about the alternative.
>
> Which would require some different code to decode what was there:
>
> int read_exception_cpu_number(ext_pt_regs *e)
> {
> if (cpu_feature_enabled(X86_FEATURE_FSGSBASE))
> return gsbase_to_cpu_number(e->ext_cpu_nr);
> else
> return e->ext_cpu_nr;
> }
>
> I'm thinking that the whole racy smp_processor_id() thing wasn't so bad
> in the first place.
prev parent reply other threads:[~2022-08-09 21:20 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-05 17:30 [RFC PATCH 0/5] Print CPU at segfault time ira.weiny
2022-08-05 17:30 ` [RFC PATCH 1/5] entry: Pass pt_regs to irqentry_exit_cond_resched() ira.weiny
2022-08-05 18:33 ` Rik van Riel
2022-08-08 10:38 ` Borislav Petkov
2022-08-08 17:34 ` Ira Weiny
2022-08-08 17:38 ` Borislav Petkov
2022-08-08 17:43 ` Dave Hansen
2022-08-08 17:52 ` Borislav Petkov
2022-08-09 23:18 ` Thomas Gleixner
2022-08-10 7:25 ` Thomas Gleixner
2022-08-05 17:30 ` [RFC PATCH 2/5] entry: Add calls for save/restore auxiliary pt_regs ira.weiny
2022-08-05 18:34 ` Rik van Riel
2022-08-09 12:05 ` Borislav Petkov
2022-08-09 18:38 ` Ira Weiny
2022-08-09 18:49 ` Borislav Petkov
2022-08-09 21:14 ` Thomas Gleixner
2022-08-09 21:38 ` Borislav Petkov
2022-08-09 22:33 ` Ira Weiny
2022-08-09 21:49 ` Ira Weiny
2022-08-09 23:53 ` Thomas Gleixner
2022-08-05 17:30 ` [RFC PATCH 3/5] x86/entry: Add auxiliary pt_regs space ira.weiny
2022-08-05 18:45 ` Rik van Riel
2022-08-05 17:30 ` [RFC PATCH 4/5] x86,mm: print likely CPU at segfault time ira.weiny
2022-08-05 17:30 ` [RFC PATCH 5/5] x86/entry: Store CPU info on exception entry ira.weiny
2022-08-05 18:46 ` Rik van Riel
2022-08-05 18:47 ` Dave Hansen
2022-08-06 9:01 ` Ingo Molnar
2022-08-06 9:11 ` Borislav Petkov
2022-08-07 10:02 ` Ingo Molnar
2022-08-07 10:35 ` Borislav Petkov
2022-08-07 20:02 ` Ira Weiny
2022-08-08 11:03 ` Ingo Molnar
2022-08-08 12:01 ` Borislav Petkov
2022-08-09 20:06 ` Thomas Gleixner
2022-08-08 16:16 ` Dave Hansen
2022-08-08 17:24 ` Rik van Riel
2022-08-09 21:19 ` Andy Lutomirski [this message]
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