From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DCA4C433E7 for ; Mon, 12 Oct 2020 16:31:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F13872080A for ; Mon, 12 Oct 2020 16:31:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="nURJ3RvF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390681AbgJLQbj (ORCPT ); Mon, 12 Oct 2020 12:31:39 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:40140 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390442AbgJLQbi (ORCPT ); Mon, 12 Oct 2020 12:31:38 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 09CGVSha023047; Mon, 12 Oct 2020 11:31:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1602520288; bh=JDeU4Uy898wDi4rKfXKDnwhxFvoNjhbCySd0iK6HaAQ=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=nURJ3RvFVIZchoS5A+rvQZm3r+Z8cmRmK7012Q52zpE4iuKK0WjcroPfrY+Tl2Ze2 Y66tB6l1KqCrNquI9dK3Cz9/moPOOFh8oNi7I4d3viZNJPmEh98Nt8adR/s5KtEx0M mUwpSEYJ6at7az0DFYEaIpNCCv+vgdVA7S8gGQiw= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 09CGVSuY095261 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 12 Oct 2020 11:31:28 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 12 Oct 2020 11:31:28 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 12 Oct 2020 11:31:28 -0500 Received: from [10.250.232.108] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 09CGVNCE112483; Mon, 12 Oct 2020 11:31:24 -0500 Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops To: Lorenzo Pieralisi CC: Rob Herring , Gustavo Pimentel , "Z.q. Hou" , "linux-kernel@vger.kernel.org" , PCI , Bjorn Helgaas , Michael Walle , Ard Biesheuvel References: <20200928093911.GB12010@e121166-lin.cambridge.arm.com> <9ac53f04-f2e8-c5f9-e1f7-e54270ec55a0@ti.com> <67ac959f-561e-d1a0-2d89-9a85d5f92c72@ti.com> <20201008150819.GA3871@e121166-lin.cambridge.arm.com> From: Kishon Vijay Abraham I Message-ID: Date: Mon, 12 Oct 2020 22:01:23 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201008150819.GA3871@e121166-lin.cambridge.arm.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Lorenzo, On 08/10/20 8:38 pm, Lorenzo Pieralisi wrote: > On Thu, Oct 01, 2020 at 07:02:04PM +0530, Kishon Vijay Abraham I wrote: > > [...] > >>>> Yeah, I don't see any registers in the DRA7x PCIe wrapper for disabling >>>> error forwarding. >>> >>> It's a DWC port logic register AFAICT, but perhaps not present in all versions. >> >> Okay. I see there's a register PCIECTRL_PL_AXIS_SLV_ERR_RESP which has a >> reset value of 0. >> >> It has four bit-fields, RESET_TIMEOUT_ERR_MAP, NO_VID_ERR_MAP, >> DBI_ERR_MAP and SLAVE_ERR_MAP. I'm not seeing any difference in behavior >> if I set all these bits. Maybe it requires platform support too. I'll >> check this with our design team. >> >> Meanwhile would it be okay to add linkup check atleast for DRA7X so that >> we could have it booting in linux-next? > > Do you mind sending a patch on top of my pci/dwc please ? I just tried applying this on your pci/dwc branch and it applied without any conflicts. Please let me know if you still want me or Hou to resend the patch. Thank you, Kishon