From: isaku.yamahata@intel.com
To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com,
Paolo Bonzini <pbonzini@redhat.com>,
erdemaktas@google.com, Sean Christopherson <seanjc@google.com>,
Sagi Shahar <sagis@google.com>
Subject: [PATCH v9 038/105] KVM: VMX: Introduce test mode related to EPT violation VE
Date: Fri, 30 Sep 2022 03:17:32 -0700 [thread overview]
Message-ID: <d24eb9c76ee3d09cb1dbfd73762591800885cc57.1664530907.git.isaku.yamahata@intel.com> (raw)
In-Reply-To: <cover.1664530907.git.isaku.yamahata@intel.com>
From: Isaku Yamahata <isaku.yamahata@intel.com>
To support TDX, KVM is enhanced to operate with #VE. For TDX, KVM programs
to inject #VE conditionally and set #VE suppress bit in EPT entry. For VMX
case, #VE isn't used. If #VE happens for VMX, it's a bug. To be
defensive (test that VMX case isn't broken), introduce option
ept_violation_ve_test and when it's set, set error.
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
---
arch/x86/include/asm/vmx.h | 12 +++++++
arch/x86/kvm/vmx/vmcs.h | 5 +++
arch/x86/kvm/vmx/vmx.c | 68 +++++++++++++++++++++++++++++++++++++-
arch/x86/kvm/vmx/vmx.h | 3 ++
4 files changed, 87 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 6231ef005a50..f0f8eecf55ac 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -68,6 +68,7 @@
#define SECONDARY_EXEC_ENCLS_EXITING VMCS_CONTROL_BIT(ENCLS_EXITING)
#define SECONDARY_EXEC_RDSEED_EXITING VMCS_CONTROL_BIT(RDSEED_EXITING)
#define SECONDARY_EXEC_ENABLE_PML VMCS_CONTROL_BIT(PAGE_MOD_LOGGING)
+#define SECONDARY_EXEC_EPT_VIOLATION_VE VMCS_CONTROL_BIT(EPT_VIOLATION_VE)
#define SECONDARY_EXEC_PT_CONCEAL_VMX VMCS_CONTROL_BIT(PT_CONCEAL_VMX)
#define SECONDARY_EXEC_XSAVES VMCS_CONTROL_BIT(XSAVES)
#define SECONDARY_EXEC_MODE_BASED_EPT_EXEC VMCS_CONTROL_BIT(MODE_BASED_EPT_EXEC)
@@ -223,6 +224,8 @@ enum vmcs_field {
VMREAD_BITMAP_HIGH = 0x00002027,
VMWRITE_BITMAP = 0x00002028,
VMWRITE_BITMAP_HIGH = 0x00002029,
+ VE_INFORMATION_ADDRESS = 0x0000202A,
+ VE_INFORMATION_ADDRESS_HIGH = 0x0000202B,
XSS_EXIT_BITMAP = 0x0000202C,
XSS_EXIT_BITMAP_HIGH = 0x0000202D,
ENCLS_EXITING_BITMAP = 0x0000202E,
@@ -628,4 +631,13 @@ enum vmx_l1d_flush_state {
extern enum vmx_l1d_flush_state l1tf_vmx_mitigation;
+struct vmx_ve_information {
+ u32 exit_reason;
+ u32 delivery;
+ u64 exit_qualification;
+ u64 guest_linear_address;
+ u64 guest_physical_address;
+ u16 eptp_index;
+};
+
#endif
diff --git a/arch/x86/kvm/vmx/vmcs.h b/arch/x86/kvm/vmx/vmcs.h
index ac290a44a693..9277676057a7 100644
--- a/arch/x86/kvm/vmx/vmcs.h
+++ b/arch/x86/kvm/vmx/vmcs.h
@@ -140,6 +140,11 @@ static inline bool is_nm_fault(u32 intr_info)
return is_exception_n(intr_info, NM_VECTOR);
}
+static inline bool is_ve_fault(u32 intr_info)
+{
+ return is_exception_n(intr_info, VE_VECTOR);
+}
+
/* Undocumented: icebp/int1 */
static inline bool is_icebp(u32 intr_info)
{
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index b53ffd367f51..f1e25e4097e1 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -126,6 +126,9 @@ module_param(error_on_inconsistent_vmcs_config, bool, 0444);
static bool __read_mostly dump_invalid_vmcs = 0;
module_param(dump_invalid_vmcs, bool, 0644);
+static bool __read_mostly ept_violation_ve_test;
+module_param(ept_violation_ve_test, bool, 0444);
+
#define MSR_BITMAP_MODE_X2APIC 1
#define MSR_BITMAP_MODE_X2APIC_APICV 2
@@ -783,6 +786,13 @@ void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu)
eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
(1u << DB_VECTOR) | (1u << AC_VECTOR);
+ /*
+ * #VE isn't used for VMX, but for TDX. To test against unexpected
+ * change related to #VE for VMX, intercept unexpected #VE and warn on
+ * it.
+ */
+ if (ept_violation_ve_test)
+ eb |= 1u << VE_VECTOR;
/*
* Guest access to VMware backdoor ports could legitimately
* trigger #GP because of TSS I/O permission bitmap.
@@ -2647,6 +2657,8 @@ static int setup_vmcs_config(struct vmcs_config *vmcs_conf,
SECONDARY_EXEC_NOTIFY_VM_EXITING;
if (cpu_has_sgx())
opt2 |= SECONDARY_EXEC_ENCLS_EXITING;
+ if (ept_violation_ve_test)
+ opt2 |= SECONDARY_EXEC_EPT_VIOLATION_VE;
if (adjust_vmx_controls(min2, opt2,
MSR_IA32_VMX_PROCBASED_CTLS2,
&_cpu_based_2nd_exec_control) < 0)
@@ -2681,6 +2693,7 @@ static int setup_vmcs_config(struct vmcs_config *vmcs_conf,
return -EIO;
vmx_cap->ept = 0;
+ _cpu_based_2nd_exec_control &= ~SECONDARY_EXEC_EPT_VIOLATION_VE;
}
if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
vmx_cap->vpid) {
@@ -4520,6 +4533,7 @@ static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
if (!enable_ept) {
exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
+ exec_control &= ~SECONDARY_EXEC_EPT_VIOLATION_VE;
enable_unrestricted_guest = 0;
}
if (!enable_unrestricted_guest)
@@ -4647,8 +4661,40 @@ static void init_vmcs(struct vcpu_vmx *vmx)
exec_controls_set(vmx, vmx_exec_control(vmx));
- if (cpu_has_secondary_exec_ctrls())
+ if (cpu_has_secondary_exec_ctrls()) {
secondary_exec_controls_set(vmx, vmx_secondary_exec_control(vmx));
+ if (secondary_exec_controls_get(vmx) &
+ SECONDARY_EXEC_EPT_VIOLATION_VE) {
+ if (!vmx->ve_info) {
+ /* ve_info must be page aligned. */
+ struct page *page;
+
+ BUILD_BUG_ON(sizeof(*vmx->ve_info) > PAGE_SIZE);
+ page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
+ if (page)
+ vmx->ve_info = page_to_virt(page);
+ }
+ if (vmx->ve_info) {
+ /*
+ * Allow #VE delivery. CPU sets this field to
+ * 0xFFFFFFFF on #VE delivery. Another #VE can
+ * occur only if software clears the field.
+ */
+ vmx->ve_info->delivery = 0;
+ vmcs_write64(VE_INFORMATION_ADDRESS,
+ __pa(vmx->ve_info));
+ } else {
+ /*
+ * Because SECONDARY_EXEC_EPT_VIOLATION_VE is
+ * used only when ept_violation_ve_test is true,
+ * it's okay to go with the bit disabled.
+ */
+ pr_err("Failed to allocate ve_info. disabling EPT_VIOLATION_VE.\n");
+ secondary_exec_controls_clearbit(vmx,
+ SECONDARY_EXEC_EPT_VIOLATION_VE);
+ }
+ }
+ }
if (cpu_has_tertiary_exec_ctrls())
tertiary_exec_controls_set(vmx, vmx_tertiary_exec_control(vmx));
@@ -5128,6 +5174,12 @@ static int handle_exception_nmi(struct kvm_vcpu *vcpu)
if (is_invalid_opcode(intr_info))
return handle_ud(vcpu);
+ /*
+ * #VE isn't supposed to happen. Although vcpu can send
+ */
+ if (KVM_BUG_ON(is_ve_fault(intr_info), vcpu->kvm))
+ return -EIO;
+
error_code = 0;
if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
@@ -6314,6 +6366,18 @@ void dump_vmcs(struct kvm_vcpu *vcpu)
if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
pr_err("Virtual processor ID = 0x%04x\n",
vmcs_read16(VIRTUAL_PROCESSOR_ID));
+ if (secondary_exec_control & SECONDARY_EXEC_EPT_VIOLATION_VE) {
+ struct vmx_ve_information *ve_info;
+
+ pr_err("VE info address = 0x%016llx\n",
+ vmcs_read64(VE_INFORMATION_ADDRESS));
+ ve_info = __va(vmcs_read64(VE_INFORMATION_ADDRESS));
+ pr_err("ve_info: 0x%08x 0x%08x 0x%016llx 0x%016llx 0x%016llx 0x%04x\n",
+ ve_info->exit_reason, ve_info->delivery,
+ ve_info->exit_qualification,
+ ve_info->guest_linear_address,
+ ve_info->guest_physical_address, ve_info->eptp_index);
+ }
}
/*
@@ -7310,6 +7374,8 @@ void vmx_vcpu_free(struct kvm_vcpu *vcpu)
free_vpid(vmx->vpid);
nested_vmx_free_vcpu(vcpu);
free_loaded_vmcs(vmx->loaded_vmcs);
+ if (vmx->ve_info)
+ free_page((unsigned long)vmx->ve_info);
}
int vmx_vcpu_create(struct kvm_vcpu *vcpu)
diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h
index c9fb46e570b0..47240671535a 100644
--- a/arch/x86/kvm/vmx/vmx.h
+++ b/arch/x86/kvm/vmx/vmx.h
@@ -359,6 +359,9 @@ struct vcpu_vmx {
DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
} shadow_msr_intercept;
+
+ /* ve_info must be page aligned. */
+ struct vmx_ve_information *ve_info;
};
struct kvm_vmx {
--
2.25.1
next prev parent reply other threads:[~2022-09-30 10:22 UTC|newest]
Thread overview: 111+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-30 10:16 [PATCH v9 000/105] KVM TDX basic feature support isaku.yamahata
2022-09-30 10:16 ` [PATCH v9 001/105] KVM: VMX: Move out vmx_x86_ops to 'main.c' to wrap VMX and TDX isaku.yamahata
2022-09-30 10:16 ` [PATCH v9 002/105] KVM: x86: Refactor KVM VMX module init/exit functions isaku.yamahata
2022-09-30 10:16 ` [PATCH v9 003/105] KVM: TDX: Add placeholders for TDX VM/vcpu structure isaku.yamahata
2022-09-30 10:16 ` [PATCH v9 004/105] x86/virt/tdx: Add a helper function to return system wide info about TDX module isaku.yamahata
2022-09-30 10:16 ` [PATCH v9 005/105] KVM: TDX: Initialize the TDX module when loading the KVM intel kernel module isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 006/105] KVM: x86: Introduce vm_type to differentiate default VMs from confidential VMs isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 007/105] KVM: TDX: Make TDX VM type supported isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 008/105] [MARKER] The start of TDX KVM patch series: TDX architectural definitions isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 009/105] KVM: TDX: Define " isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 010/105] KVM: TDX: Add TDX "architectural" error codes isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 011/105] KVM: TDX: Add C wrapper functions for SEAMCALLs to the TDX module isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 012/105] KVM: TDX: Add helper functions to print TDX SEAMCALL error isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 013/105] [MARKER] The start of TDX KVM patch series: TD VM creation/destruction isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 014/105] KVM: TDX: Stub in tdx.h with structs, accessors, and VMCS helpers isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 015/105] x86/cpu: Add helper functions to allocate/free TDX private host key id isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 016/105] KVM: TDX: create/destroy VM structure isaku.yamahata
2022-10-12 22:30 ` Sagi Shahar
2022-10-13 8:55 ` Isaku Yamahata
2022-09-30 10:17 ` [PATCH v9 017/105] KVM: TDX: Refuse to unplug the last cpu on the package isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 018/105] KVM: TDX: x86: Add ioctl to get TDX systemwide parameters isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 019/105] KVM: TDX: Add place holder for TDX VM specific mem_enc_op ioctl isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 020/105] KVM: TDX: initialize VM with TDX specific parameters isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 021/105] KVM: TDX: Make pmu_intel.c ignore guest TD case isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 022/105] [MARKER] The start of TDX KVM patch series: TD vcpu creation/destruction isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 023/105] KVM: TDX: allocate/free TDX vcpu structure isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 024/105] KVM: TDX: Do TDX specific vcpu initialization isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 025/105] KVM: TDX: Use private memory for TDX isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 026/105] [MARKER] The start of TDX KVM patch series: KVM MMU GPA shared bits isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 027/105] KVM: x86/mmu: introduce config for PRIVATE KVM MMU isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 028/105] KVM: x86/mmu: Add address conversion functions for TDX shared bit of GPA isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 029/105] [MARKER] The start of TDX KVM patch series: KVM TDP refactoring for TDX isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 030/105] KVM: x86/mmu: Replace hardcoded value 0 for the initial value for SPTE isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 031/105] KVM: x86/mmu: Make sync_page not use hard-coded 0 as the initial SPTE value isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 032/105] KVM: x86/mmu: Allow non-zero value for non-present SPTE and removed SPTE isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 033/105] KVM: x86/mmu: Add Suppress VE bit to shadow_mmio_{value, mask} isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 034/105] KVM: x86/mmu: Track shadow MMIO value on a per-VM basis isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 035/105] KVM: TDX: Enable mmio spte caching always for TDX isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 036/105] KVM: x86/mmu: Disallow fast page fault on private GPA isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 037/105] KVM: x86/mmu: Allow per-VM override of the TDP max page level isaku.yamahata
2022-09-30 10:17 ` isaku.yamahata [this message]
2022-09-30 10:17 ` [PATCH v9 039/105] [MARKER] The start of TDX KVM patch series: KVM TDP MMU hooks isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 040/105] KVM: x86/tdp_mmu: refactor kvm_tdp_mmu_map() isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 041/105] KVM: x86/tdp_mmu: Init role member of struct kvm_mmu_page at allocation isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 042/105] KVM: x86/mmu: Require TDP MMU for TDX isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 043/105] KVM: x86/mmu: Add a new is_private member for union kvm_mmu_page_role isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 044/105] KVM: x86/mmu: Add a private pointer to struct kvm_mmu_page isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 045/105] KVM: x86/tdp_mmu: Don't zap private pages for unsupported cases isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 046/105] KVM: x86/tdp_mmu: Support TDX private mapping for TDP MMU isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 047/105] [MARKER] The start of TDX KVM patch series: TDX EPT violation isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 048/105] KVM: x86/mmu: Disallow dirty logging for x86 TDX isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 049/105] KVM: x86/tdp_mmu: Ignore unsupported mmu operation on private GFNs isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 050/105] KVM: VMX: Split out guts of EPT violation to common/exposed function isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 051/105] KVM: VMX: Move setting of EPT MMU masks to common VT-x code isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 052/105] KVM: TDX: Add load_mmu_pgd method for TDX isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 053/105] KVM: TDX: don't request KVM_REQ_APIC_PAGE_RELOAD isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 054/105] KVM: x86/VMX: introduce vmx tlb_remote_flush and tlb_remote_flush_with_range isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 055/105] KVM: TDX: TDP MMU TDX support isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 056/105] [MARKER] The start of TDX KVM patch series: KVM TDP MMU MapGPA isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 057/105] KVM: Add functions to set GFN to private or shared isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 058/105] KVM: x86/mmu: Introduce kvm_mmu_map_tdp_page() for use by TDX isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 059/105] KVM: x86/tdp_mmu: implement MapGPA hypercall for TDX isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 060/105] [MARKER] The start of TDX KVM patch series: TD finalization isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 061/105] KVM: TDX: Create initial guest memory isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 062/105] KVM: TDX: Finalize VM initialization isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 063/105] [MARKER] The start of TDX KVM patch series: TD vcpu enter/exit isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 064/105] KVM: TDX: Add helper assembly function to TDX vcpu isaku.yamahata
2022-09-30 10:17 ` [PATCH v9 065/105] KVM: TDX: Implement TDX vcpu enter/exit path isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 066/105] KVM: TDX: vcpu_run: save/restore host state(host kernel gs) isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 067/105] KVM: TDX: restore host xsave state when exit from the guest TD isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 068/105] KVM: x86: Allow to update cached values in kvm_user_return_msrs w/o wrmsr isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 069/105] KVM: TDX: restore user ret MSRs isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 070/105] [MARKER] The start of TDX KVM patch series: TD vcpu exits/interrupts/hypercalls isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 071/105] KVM: TDX: complete interrupts after tdexit isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 072/105] KVM: TDX: restore debug store when TD exit isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 073/105] KVM: TDX: handle vcpu migration over logical processor isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 074/105] KVM: x86: Add a switch_db_regs flag to handle TDX's auto-switched behavior isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 075/105] KVM: TDX: Add support for find pending IRQ in a protected local APIC isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 076/105] KVM: x86: Assume timer IRQ was injected if APIC state is proteced isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 077/105] KVM: TDX: remove use of struct vcpu_vmx from posted_interrupt.c isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 078/105] KVM: TDX: Implement interrupt injection isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 079/105] KVM: TDX: Implements vcpu request_immediate_exit isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 080/105] KVM: TDX: Implement methods to inject NMI isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 081/105] KVM: VMX: Modify NMI and INTR handlers to take intr_info as function argument isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 082/105] KVM: VMX: Move NMI/exception handler to common helper isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 083/105] KVM: x86: Split core of hypercall emulation to helper function isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 084/105] KVM: TDX: Add a place holder to handle TDX VM exit isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 085/105] KVM: TDX: Retry seamcall when TDX_OPERAND_BUSY with operand SEPT isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 086/105] KVM: TDX: handle EXIT_REASON_OTHER_SMI isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 087/105] KVM: TDX: handle ept violation/misconfig exit isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 088/105] KVM: TDX: handle EXCEPTION_NMI and EXTERNAL_INTERRUPT isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 089/105] KVM: TDX: Add a place holder for handler of TDX hypercalls (TDG.VP.VMCALL) isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 090/105] KVM: TDX: handle KVM hypercall with TDG.VP.VMCALL isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 091/105] KVM: TDX: Handle TDX PV CPUID hypercall isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 092/105] KVM: TDX: Handle TDX PV HLT hypercall isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 093/105] KVM: TDX: Handle TDX PV port io hypercall isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 094/105] KVM: TDX: Handle TDX PV MMIO hypercall isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 095/105] KVM: TDX: Implement callbacks for MSR operations for TDX isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 096/105] KVM: TDX: Handle TDX PV rdmsr/wrmsr hypercall isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 097/105] KVM: TDX: Handle TDX PV report fatal error hypercall isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 098/105] KVM: TDX: Handle TDX PV map_gpa hypercall isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 099/105] KVM: TDX: Handle TDG.VP.VMCALL<GetTdVmCallInfo> hypercall isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 100/105] KVM: TDX: Silently discard SMI request isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 101/105] KVM: TDX: Silently ignore INIT/SIPI isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 102/105] KVM: TDX: Add methods to ignore accesses to CPU state isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 103/105] Documentation/virt/kvm: Document on Trust Domain Extensions(TDX) isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 104/105] KVM: x86: design documentation on TDX support of x86 KVM TDP MMU isaku.yamahata
2022-09-30 10:18 ` [PATCH v9 105/105] [MARKER] the end of (the first phase of) TDX KVM patch series isaku.yamahata
2022-10-01 8:30 ` [PATCH v9 000/105] KVM TDX basic feature support Bagas Sanjaya
2022-10-03 18:29 ` Isaku Yamahata
2022-10-03 20:08 ` Huang, Kai
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=d24eb9c76ee3d09cb1dbfd73762591800885cc57.1664530907.git.isaku.yamahata@intel.com \
--to=isaku.yamahata@intel.com \
--cc=erdemaktas@google.com \
--cc=isaku.yamahata@gmail.com \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=pbonzini@redhat.com \
--cc=sagis@google.com \
--cc=seanjc@google.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).