From: Marek Vasut <marex@denx.de>
To: Joel Holdsworth <joel@airwebreathe.org.uk>,
Moritz Fischer <moritz.fischer@ettus.com>
Cc: Alan Tull <atull@opensource.altera.com>,
Geert Uytterhoeven <geert@linux-m68k.org>,
Rob Herring <robh@kernel.org>,
Devicetree List <devicetree@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-spi@vger.kernel.org, Clifford Wolf <clifford@clifford.at>
Subject: Re: [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs
Date: Thu, 10 Nov 2016 13:11:08 +0100 [thread overview]
Message-ID: <d2902132-2745-b9f6-5799-ffd3db96941d@denx.de> (raw)
In-Reply-To: <d3af549a-0f68-7511-ad38-b9ec8aab62ca@airwebreathe.org.uk>
On 11/09/2016 07:54 PM, Joel Holdsworth wrote:
> On 09/11/16 11:39, Marek Vasut wrote:
>> On 11/09/2016 07:37 PM, Joel Holdsworth wrote:
>>> On 09/11/16 05:01, Marek Vasut wrote:
>>>> On 11/08/2016 06:30 PM, Joel Holdsworth wrote:
>>>>>>>> On the whole, I don't think the zero-length transfers are too
>>>>>>>> egregiously bad, and all the alternatives seem worse to me.
>>>>>>>
>>>>>>> So why not turn the CS line into GPIO and just toggle the GPIO?
>>>>>>
>>>>>> Does that work with *all* SPI controllers?
>>>>>>
>>>>>
>>>>> It does not - no. See my other email.
>>>>
>>>> And is that line an actual CS of that lattice chip or a generic input
>>>> which almost works like CS?
>>>>
>>>
>>> I mean a generic output vs. a special CS output built into the SPI
>>> master of the application processor. Take a look at how spi_set_cs(..)
>>> works:
>>
>> No. I am asking whether the signal which is INPUT on the iCE40 side is
>> really a chipselect signal for the SPI bus OR something which mostly
>> behaves/looks like a chipselect but is not really a chipselect.
>
> Oh I see. The SS_B line is the SPI SlaveSelect for the configuration port.
>
> This is the text from the datasheet:
>
> "SPI Slave Select. Active Low. Includes an internal weak pull-up
> resistor to VCC_SPI during configuration. During configuration, the
> logic level sampled on this pin deter-mines the configuration mode used
> by the iCE40 device. An input when sampled at the start of
> configuration. An input when in SPI Peripheral configuration mode
> (SPI_SS_B = Low). An output when in Master SPI Flash configuration mode."
>
> So yes - it is a "real" SPI chip-select line.
OK, thanks for checking.
--
Best regards,
Marek Vasut
next prev parent reply other threads:[~2016-11-10 16:52 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-07 2:49 [PATCH v8 1/3] of: Add vendor prefix for Lattice Semiconductor Joel Holdsworth
2016-11-07 2:49 ` [PATCH v8 2/3] Documentation: Add binding document for Lattice iCE40 FPGA manager Joel Holdsworth
2016-11-07 17:53 ` Marek Vasut
2016-11-07 18:57 ` Joel Holdsworth
2016-11-14 16:11 ` Rob Herring
2016-11-18 18:56 ` atull
2016-11-18 19:17 ` Moritz Fischer
2016-11-18 19:28 ` Marek Vasut
2016-11-07 2:49 ` [PATCH v8 3/3] fpga: Add support for Lattice iCE40 FPGAs Joel Holdsworth
2016-11-07 18:01 ` Marek Vasut
2016-11-07 18:49 ` Joel Holdsworth
2016-11-07 18:53 ` Marek Vasut
2016-11-08 17:06 ` Moritz Fischer
2016-11-08 17:30 ` Joel Holdsworth
2016-11-09 12:01 ` Marek Vasut
2016-11-09 18:37 ` Joel Holdsworth
2016-11-09 18:39 ` Marek Vasut
2016-11-09 18:54 ` Joel Holdsworth
2016-11-10 12:11 ` Marek Vasut [this message]
2016-11-08 17:13 ` Joel Holdsworth
2016-11-07 18:26 ` Moritz Fischer
2016-11-07 19:02 ` Joel Holdsworth
2016-11-07 21:41 ` Moritz Fischer
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