From: Rajendra Nayak <rnayak@codeaurora.org>
To: Matthias Kaehlcke <mka@chromium.org>
Cc: viresh.kumar@linaro.org, sboyd@kernel.org,
bjorn.andersson@linaro.org, agross@kernel.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Akash Asthana <akashast@codeaurora.org>,
linux-serial@vger.kernel.org
Subject: Re: [PATCH 02/21] tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state
Date: Mon, 13 Apr 2020 19:28:39 +0530 [thread overview]
Message-ID: <e3aa9e6f-14f5-de51-7087-094b5089d16b@codeaurora.org> (raw)
In-Reply-To: <20200409174511.GS199755@google.com>
Hi Matthias,
On 4/9/2020 11:15 PM, Matthias Kaehlcke wrote:
> Hi Rajendra,
>
> On Wed, Apr 08, 2020 at 07:16:28PM +0530, Rajendra Nayak wrote:
>> geni serial needs to express a perforamnce state requirement on CX
>> depending on the frequency of the clock rates. Use OPP table from
>> DT to register with OPP framework and use dev_pm_opp_set_rate() to
>> set the clk/perf state.
>>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> Cc: Akash Asthana <akashast@codeaurora.org>
>> Cc: linux-serial@vger.kernel.org
>> ---
>> drivers/tty/serial/qcom_geni_serial.c | 20 +++++++++++++++-----
>> include/linux/qcom-geni-se.h | 2 ++
>> 2 files changed, 17 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
>> index 6119090..754eaf6 100644
>> --- a/drivers/tty/serial/qcom_geni_serial.c
>> +++ b/drivers/tty/serial/qcom_geni_serial.c
>> @@ -9,6 +9,7 @@
>> #include <linux/module.h>
>> #include <linux/of.h>
>> #include <linux/of_device.h>
>> +#include <linux/pm_opp.h>
>> #include <linux/platform_device.h>
>> #include <linux/pm_runtime.h>
>> #include <linux/pm_wakeirq.h>
>> @@ -961,7 +962,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
>> goto out_restart_rx;
>>
>> uport->uartclk = clk_rate;
>> - clk_set_rate(port->se.clk, clk_rate);
>> + dev_pm_opp_set_rate(uport->dev, clk_rate);
>> ser_clk_cfg = SER_CLK_EN;
>> ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
>>
>> @@ -1198,8 +1199,10 @@ static void qcom_geni_serial_pm(struct uart_port *uport,
>> if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
>> geni_se_resources_on(&port->se);
>> else if (new_state == UART_PM_STATE_OFF &&
>> - old_state == UART_PM_STATE_ON)
>> + old_state == UART_PM_STATE_ON) {
>> + dev_pm_opp_set_rate(uport->dev, 0);
>> geni_se_resources_off(&port->se);
>> + }
>> }
>>
>> static const struct uart_ops qcom_geni_console_pops = {
>> @@ -1318,13 +1321,16 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
>> if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
>> port->cts_rts_swap = true;
>>
>> + port->se.opp = dev_pm_opp_set_clkname(&pdev->dev, "se");
>
> dev_pm_opp_set_clkname() can fail for multiple reasons, it seems an error
> check would be warranted.
right, looks like I should put some error check there
> Is it actually necessary to save the OPP table in 'struct geni_se'? Both
> the serial and the SPI driver save the table, but don't use it later (nor
> does the SE driver).
I think I did that initially because I wanted to use that to call into
dev_pm_opp_put_clkname during cleanup. That however never worked since
the way the clk_put is done in dev_pm_opp_put_clkname() and _opp_table_kref_release()
seems buggy. I kind of forgot about fixing it up, I will figure our whats the right
way to do it, and either not call dev_pm_opp_put_clkname() or not store the
opp table returned by it.
thanks for taking time to review.
- Rajendra
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2020-04-13 13:58 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-08 13:46 [PATCH 00/21] DVFS for IO devices on sdm845 and sc7180 Rajendra Nayak
2020-04-08 13:46 ` [PATCH 01/21] opp: Manage empty OPP tables with clk handle Rajendra Nayak
2020-04-09 7:57 ` Viresh Kumar
2020-04-13 10:34 ` Rajendra Nayak
2020-04-13 10:42 ` Viresh Kumar
2020-04-14 6:57 ` Viresh Kumar
2020-04-08 13:46 ` [PATCH 02/21] tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-09 17:45 ` Matthias Kaehlcke
2020-04-10 8:36 ` Jun Nie
2020-04-13 14:22 ` Rajendra Nayak
2020-04-14 5:26 ` Jun Nie
2020-04-13 13:58 ` Rajendra Nayak [this message]
2020-04-10 6:56 ` Akash Asthana
2020-04-10 12:52 ` Akash Asthana
2020-04-13 14:13 ` Rajendra Nayak
2020-04-08 13:46 ` [PATCH 03/21] spi: spi-geni-qcom: " Rajendra Nayak
2020-04-09 18:20 ` Matthias Kaehlcke
2020-04-13 14:02 ` Rajendra Nayak
2020-04-08 13:46 ` [PATCH 04/21] arm64: dts: sdm845: Add OPP table for all qup devices Rajendra Nayak
2020-04-08 13:46 ` [PATCH 05/21] arm64: dts: sc7180: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 06/21] scsi: ufs: Add support to manage multiple power domains in ufshcd-pltfrm Rajendra Nayak
2020-04-08 13:46 ` [PATCH 07/21] scsi: ufs: Add support for specifying OPP tables in DT Rajendra Nayak
2020-04-08 13:46 ` [PATCH 08/21] arm64: dts: sdm845: Add ufs opps and power-domains Rajendra Nayak
2020-04-08 13:46 ` [PATCH 09/21] drm/msm/dpu: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-08 13:46 ` [PATCH 10/21] drm/msm: dsi: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 11/21] arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domains Rajendra Nayak
2020-04-08 13:46 ` [PATCH 12/21] arm64: dts: sc7180: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 13/21] mmc: sdhci-msm: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-15 13:52 ` Ulf Hansson
2020-04-15 16:43 ` Rajendra Nayak
2020-04-16 3:39 ` Viresh Kumar
2020-04-16 8:21 ` Ulf Hansson
2020-04-16 8:23 ` Ulf Hansson
2020-04-08 13:46 ` [PATCH 14/21] arm64: dts: sdm845: Add sdhc opps and power-domains Rajendra Nayak
2020-04-08 13:46 ` [PATCH 15/21] arm64: dts: sc7180: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 16/21] media: venus: core: Add support for opp tables/perf voting Rajendra Nayak
2020-04-08 13:46 ` [PATCH 17/21] arm64: dts: sdm845: Add OPP tables and power-domains for venus Rajendra Nayak
2020-04-08 13:46 ` [PATCH 18/21] arm64: dts: sc7180: " Rajendra Nayak
2020-04-08 13:46 ` [PATCH 19/21] spi: spi-qcom-qspi: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-08 13:46 ` [PATCH 20/21] arm64: dts: sdm845: Add qspi opps and power-domains Rajendra Nayak
2020-04-08 13:46 ` [PATCH 21/21] arm64: dts: sc7180: " Rajendra Nayak
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e3aa9e6f-14f5-de51-7087-094b5089d16b@codeaurora.org \
--to=rnayak@codeaurora.org \
--cc=agross@kernel.org \
--cc=akashast@codeaurora.org \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-serial@vger.kernel.org \
--cc=mka@chromium.org \
--cc=sboyd@kernel.org \
--cc=viresh.kumar@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).