From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C338C2D0A3 for ; Sat, 24 Oct 2020 12:44:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 23B922225E for ; Sat, 24 Oct 2020 12:44:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="CVKQfsBW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761482AbgJXMop (ORCPT ); Sat, 24 Oct 2020 08:44:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1761470AbgJXMom (ORCPT ); Sat, 24 Oct 2020 08:44:42 -0400 Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:8b0:10b:1231::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95961C0613CE; Sat, 24 Oct 2020 05:44:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=merlin.20170209; h=Mime-Version:Content-Type:References: In-Reply-To:Date:Cc:To:From:Subject:Message-ID:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=ytbzsY3MYQoB07gSB/iQyxjHhNuMGuPQzQqfVAZ6KjA=; b=CVKQfsBWJf2JcKvak0oGMmGN8X wT61DJLLknf/JQyT6ajXF/rsSTJp8dRxxT51SQ2AwtCZIQ1ga/Y+LQgvTkHXlUrYjTAc6Y2akT5IQ b0ii8QuFw0/bUKcT3ojRMPWRJa7Xu0XXwV2brgdm6nyzVy5RAD3AXBtNd3VwN/d3ZfKSHtUdRd3xh iWozLpwYIfqdGuDZqhgPsUkHe3RsDg/L+c9TUYoUbJvj+9Qpg/cHVzGwdAaKM8gpsQSsW8LdTsVAi yFbuOe+eUKdg9BSZM+B5LDdUr0BM1HHb9IXWFQ+92Hf0CZDH6vJgZt1Yd1pv/C/3WQsgwLKPJL3IH et+KKixw==; Received: from dyn-227.woodhou.se ([90.155.92.227]) by merlin.infradead.org with esmtpsa (Exim 4.92.3 #3 (Red Hat Linux)) id 1kWIuQ-0005yo-Oo; Sat, 24 Oct 2020 12:44:35 +0000 Message-ID: Subject: Re: [PATCH v2 8/8] x86/ioapic: Generate RTE directly from parent irqchip's MSI message From: David Woodhouse To: Paolo Bonzini , Thomas Gleixner , x86@kernel.org Cc: kvm , linux-kernel , linux-hyperv@vger.kernel.org, Dexuan Cui Date: Sat, 24 Oct 2020 13:44:32 +0100 In-Reply-To: References: <87y2jy542v.fsf@nanos.tec.linutronix.de> <87d01863a2.fsf@nanos.tec.linutronix.de> Content-Type: multipart/signed; micalg="sha-256"; protocol="application/x-pkcs7-signature"; boundary="=-jngacfh4zQtjAO6UD6YJ" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 Mime-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by merlin.infradead.org. See http://www.infradead.org/rpr.html Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-jngacfh4zQtjAO6UD6YJ Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sat, 2020-10-24 at 11:13 +0100, David Woodhouse wrote: > OK, thanks. I'll rework Thomas's tree with that first and the other > changes I'd mentioned in my parts, as well as fixing up that unholy > chim=C3=A6ra of struct/union in which we set some bitfields from each sid= e > of the union, test and push it out later today. OK, pushed out to=20 https://git.infradead.org/users/dwmw2/linux.git/shortlog/refs/heads/x86/api= c] It's Thomas's tree plus the struct/union fixes and other things I mentioned earlier, a few comment fixes in the 'Generate RTE directly from parent irqchip' patch, but the most interesting part is finishing the job of the 'Cleanup IO/APIC route entry structs' patch... =46rom 54b623fc2b03eadb76485b4ca0ade3e79acf6c27 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Thu, 22 Oct 2020 14:48:18 +0200 Subject: [PATCH 124/137] x86/ioapic: Cleanup IO/APIC route entry structs Having two seperate structs for the I/O-APIC RTE entries (non-remapped and DMAR remapped) requires type casts and makes it hard to map. Combine them in IO_APIC_routing_entry by defining a union of two 64bit bitfields. Use naming which reflects which bits are shared and which bits are actually different for the operating modes. [dwmw2: Fix it up and finish the job, pulling the 32-bit w1,w2 words for register access into the same union and eliminating a few more places where bits were accessed through masks and shifts.] Signed-off-by: Thomas Gleixner Signed-off-by: David Woodhouse --- arch/x86/include/asm/io_apic.h | 78 ++++++--------- arch/x86/kernel/apic/io_apic.c | 144 +++++++++++++--------------- drivers/iommu/amd/iommu.c | 8 +- drivers/iommu/hyperv-iommu.c | 4 +- drivers/iommu/intel/irq_remapping.c | 19 ++-- 5 files changed, 108 insertions(+), 145 deletions(-) diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.= h index a1a26f6d3aa4..73da644b2f0d 100644 --- a/arch/x86/include/asm/io_apic.h +++ b/arch/x86/include/asm/io_apic.h @@ -13,15 +13,6 @@ * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar */ =20 -/* I/O Unit Redirection Table */ -#define IO_APIC_REDIR_VECTOR_MASK 0x000FF -#define IO_APIC_REDIR_DEST_LOGICAL 0x00800 -#define IO_APIC_REDIR_DEST_PHYSICAL 0x00000 -#define IO_APIC_REDIR_SEND_PENDING (1 << 12) -#define IO_APIC_REDIR_REMOTE_IRR (1 << 14) -#define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15) -#define IO_APIC_REDIR_MASKED (1 << 16) - /* * The structure of the IO-APIC: */ @@ -65,52 +56,39 @@ union IO_APIC_reg_03 { }; =20 struct IO_APIC_route_entry { - __u32 vector : 8, - delivery_mode : 3, /* 000: FIXED - * 001: lowest prio - * 111: ExtINT - */ - dest_mode : 1, /* 0: physical, 1: logical */ - delivery_status : 1, - polarity : 1, - irr : 1, - trigger : 1, /* 0: edge, 1: level */ - mask : 1, /* 0: enabled, 1: disabled */ - __reserved_2 : 15; - - __u32 __reserved_3 : 24, - dest : 8; -} __attribute__ ((packed)); - -struct IR_IO_APIC_route_entry { - __u64 vector : 8, - zero : 3, - index2 : 1, - delivery_status : 1, - polarity : 1, - irr : 1, - trigger : 1, - mask : 1, - reserved : 31, - format : 1, - index : 15; + union { + struct { + u64 vector : 8, + delivery_mode : 3, + dest_mode_logical : 1, + delivery_status : 1, + active_low : 1, + irr : 1, + is_level : 1, + masked : 1, + reserved_0 : 15, + reserved_1 : 24, + destid_0_7 : 8; + }; + struct { + u64 ir_shared_0 : 8, + ir_zero : 3, + ir_index_15 : 1, + ir_shared_1 : 5, + ir_reserved_0 : 31, + ir_format : 1, + ir_index_0_14 : 15; + }; + struct { + u64 w1 : 32, + w2 : 32; + }; + }; } __attribute__ ((packed)); =20 struct irq_alloc_info; struct ioapic_domain_cfg; =20 -#define IOAPIC_EDGE 0 -#define IOAPIC_LEVEL 1 - -#define IOAPIC_MASKED 1 -#define IOAPIC_UNMASKED 0 - -#define IOAPIC_POL_HIGH 0 -#define IOAPIC_POL_LOW 1 - -#define IOAPIC_DEST_MODE_PHYSICAL 0 -#define IOAPIC_DEST_MODE_LOGICAL 1 - #define IOAPIC_MAP_ALLOC 0x1 #define IOAPIC_MAP_CHECK 0x2 =20 diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.= c index 24a7bba7cbf4..07e754131854 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -286,31 +286,26 @@ static void io_apic_write(unsigned int apic, unsigned= int reg, writel(value, &io_apic->data); } =20 -union entry_union { - struct { u32 w1, w2; }; - struct IO_APIC_route_entry entry; -}; - static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) { - union entry_union eu; + struct IO_APIC_route_entry entry; =20 - eu.w1 =3D io_apic_read(apic, 0x10 + 2 * pin); - eu.w2 =3D io_apic_read(apic, 0x11 + 2 * pin); + entry.w1 =3D io_apic_read(apic, 0x10 + 2 * pin); + entry.w2 =3D io_apic_read(apic, 0x11 + 2 * pin); =20 - return eu.entry; + return entry; } =20 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) { - union entry_union eu; + struct IO_APIC_route_entry entry; unsigned long flags; =20 raw_spin_lock_irqsave(&ioapic_lock, flags); - eu.entry =3D __ioapic_read_entry(apic, pin); + entry =3D __ioapic_read_entry(apic, pin); raw_spin_unlock_irqrestore(&ioapic_lock, flags); =20 - return eu.entry; + return entry; } =20 /* @@ -321,11 +316,8 @@ static struct IO_APIC_route_entry ioapic_read_entry(in= t apic, int pin) */ static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_e= ntry e) { - union entry_union eu =3D {{0, 0}}; - - eu.entry =3D e; - io_apic_write(apic, 0x11 + 2*pin, eu.w2); - io_apic_write(apic, 0x10 + 2*pin, eu.w1); + io_apic_write(apic, 0x11 + 2*pin, e.w2); + io_apic_write(apic, 0x10 + 2*pin, e.w1); } =20 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_ent= ry e) @@ -344,12 +336,12 @@ static void ioapic_write_entry(int apic, int pin, str= uct IO_APIC_route_entry e) */ static void ioapic_mask_entry(int apic, int pin) { + struct IO_APIC_route_entry e =3D { .masked =3D true }; unsigned long flags; - union entry_union eu =3D { .entry.mask =3D IOAPIC_MASKED }; =20 raw_spin_lock_irqsave(&ioapic_lock, flags); - io_apic_write(apic, 0x10 + 2*pin, eu.w1); - io_apic_write(apic, 0x11 + 2*pin, eu.w2); + io_apic_write(apic, 0x10 + 2*pin, e.w1); + io_apic_write(apic, 0x11 + 2*pin, e.w2); raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 @@ -422,20 +414,15 @@ static void __init replace_pin_at_irq_node(struct mp_= chip_data *data, int node, add_pin_to_irq_node(data, node, newapic, newpin); } =20 -static void io_apic_modify_irq(struct mp_chip_data *data, - int mask_and, int mask_or, +static void io_apic_modify_irq(struct mp_chip_data *data, bool masked, void (*final)(struct irq_pin_list *entry)) { - union entry_union eu; struct irq_pin_list *entry; =20 - eu.entry =3D data->entry; - eu.w1 &=3D mask_and; - eu.w1 |=3D mask_or; - data->entry =3D eu.entry; + data->entry.masked =3D masked; =20 for_each_irq_pin(entry, data->irq_2_pin) { - io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1); + io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1); if (final) final(entry); } @@ -459,13 +446,13 @@ static void mask_ioapic_irq(struct irq_data *irq_data= ) unsigned long flags; =20 raw_spin_lock_irqsave(&ioapic_lock, flags); - io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); + io_apic_modify_irq(data, true, &io_apic_sync); raw_spin_unlock_irqrestore(&ioapic_lock, flags); } =20 static void __unmask_ioapic(struct mp_chip_data *data) { - io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL); + io_apic_modify_irq(data, false, NULL); } =20 static void unmask_ioapic_irq(struct irq_data *irq_data) @@ -506,8 +493,8 @@ static void __eoi_ioapic_pin(int apic, int pin, int vec= tor) /* * Mask the entry and change the trigger mode to edge. */ - entry1.mask =3D IOAPIC_MASKED; - entry1.trigger =3D IOAPIC_EDGE; + entry1.masked =3D true; + entry1.is_level =3D false; =20 __ioapic_write_entry(apic, pin, entry1); =20 @@ -542,8 +529,8 @@ static void clear_IO_APIC_pin(unsigned int apic, unsign= ed int pin) * Make sure the entry is masked and re-read the contents to check * if it is a level triggered pin and if the remote-IRR is set. */ - if (entry.mask =3D=3D IOAPIC_UNMASKED) { - entry.mask =3D IOAPIC_MASKED; + if (!entry.masked) { + entry.masked =3D true; ioapic_write_entry(apic, pin, entry); entry =3D ioapic_read_entry(apic, pin); } @@ -556,8 +543,8 @@ static void clear_IO_APIC_pin(unsigned int apic, unsign= ed int pin) * doesn't clear the remote-IRR if the trigger mode is not * set to level. */ - if (entry.trigger =3D=3D IOAPIC_EDGE) { - entry.trigger =3D IOAPIC_LEVEL; + if (!entry.is_level) { + entry.is_level =3D true; ioapic_write_entry(apic, pin, entry); } raw_spin_lock_irqsave(&ioapic_lock, flags); @@ -659,8 +646,8 @@ void mask_ioapic_entries(void) struct IO_APIC_route_entry entry; =20 entry =3D ioapics[apic].saved_registers[pin]; - if (entry.mask =3D=3D IOAPIC_UNMASKED) { - entry.mask =3D IOAPIC_MASKED; + if (!entry.masked) { + entry.masked =3D true; ioapic_write_entry(apic, pin, entry); } } @@ -947,8 +934,8 @@ static bool mp_check_pin_attr(int irq, struct irq_alloc= _info *info) if (irq < nr_legacy_irqs() && data->count =3D=3D 1) { if (info->ioapic.is_level !=3D data->is_level) mp_register_handler(irq, info->ioapic.is_level); - data->entry.trigger =3D data->is_level =3D info->ioapic.is_level; - data->entry.polarity =3D data->active_low =3D info->ioapic.active_low; + data->entry.is_level =3D data->is_level =3D info->ioapic.is_level; + data->entry.active_low =3D data->active_low =3D info->ioapic.active_low; } =20 return data->is_level =3D=3D info->ioapic.is_level && @@ -1231,10 +1218,9 @@ void ioapic_zap_locks(void) =20 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entri= es) { - int i; - char buf[256]; struct IO_APIC_route_entry entry; - struct IR_IO_APIC_route_entry *ir_entry =3D (void *)&entry; + char buf[256]; + int i; =20 printk(KERN_DEBUG "IOAPIC %d:\n", apic); for (i =3D 0; i <=3D nr_entries; i++) { @@ -1242,20 +1228,20 @@ static void io_apic_print_entries(unsigned int apic= , unsigned int nr_entries) snprintf(buf, sizeof(buf), " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)", i, - entry.mask =3D=3D IOAPIC_MASKED ? "disabled" : "enabled ", - entry.trigger =3D=3D IOAPIC_LEVEL ? "level" : "edge ", - entry.polarity =3D=3D IOAPIC_POL_LOW ? "low " : "high", + entry.masked ? "disabled" : "enabled ", + entry.is_level ? "level" : "edge ", + entry.active_low ? "low " : "high", entry.vector, entry.irr, entry.delivery_status); - if (ir_entry->format) + if (entry.ir_format) { printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n", - buf, (ir_entry->index2 << 15) | ir_entry->index, - ir_entry->zero); - else - printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n", buf, - entry.dest_mode =3D=3D IOAPIC_DEST_MODE_LOGICAL ? - "logical " : "physical", - entry.dest, entry.delivery_mode); + (entry.ir_index_15 << 15) | entry.ir_index_0_14, + entry.ir_zero); + } else { + printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n", buf, + entry.dest_mode_logical ? "logical " : "physical", + entry.destid_0_7, entry.delivery_mode); + } } } =20 @@ -1380,8 +1366,8 @@ void __init enable_IO_APIC(void) /* If the interrupt line is enabled and in ExtInt mode * I have found the pin where the i8259 is connected. */ - if ((entry.mask =3D=3D 0) && - (entry.delivery_mode =3D=3D APIC_DELIVERY_MODE_EXTINT)) { + if (!entry.masked && + entry.delivery_mode =3D=3D APIC_DELIVERY_MODE_EXTINT) { ioapic_i8259.apic =3D apic; ioapic_i8259.pin =3D pin; goto found_i8259; @@ -1425,12 +1411,12 @@ void native_restore_boot_irq_mode(void) struct IO_APIC_route_entry entry; =20 memset(&entry, 0, sizeof(entry)); - entry.mask =3D IOAPIC_UNMASKED; - entry.trigger =3D IOAPIC_EDGE; - entry.polarity =3D IOAPIC_POL_HIGH; - entry.dest_mode =3D IOAPIC_DEST_MODE_PHYSICAL; + entry.masked =3D false; + entry.is_level =3D false; + entry.active_low =3D false; + entry.dest_mode_logical =3D false; entry.delivery_mode =3D APIC_DELIVERY_MODE_EXTINT; - entry.dest =3D read_apic_id(); + entry.destid_0_7 =3D read_apic_id(); =20 /* * Add it to the IO-APIC irq-routing table: @@ -1709,13 +1695,13 @@ static bool io_apic_level_ack_pending(struct mp_chi= p_data *data) =20 raw_spin_lock_irqsave(&ioapic_lock, flags); for_each_irq_pin(entry, data->irq_2_pin) { - unsigned int reg; + struct IO_APIC_route_entry e; int pin; =20 pin =3D entry->pin; - reg =3D io_apic_read(entry->apic, 0x10 + pin*2); + e.w1 =3D io_apic_read(entry->apic, 0x10 + pin*2); /* Is the remote IRR bit set? */ - if (reg & IO_APIC_REDIR_REMOTE_IRR) { + if (e.irr) { raw_spin_unlock_irqrestore(&ioapic_lock, flags); return true; } @@ -1874,7 +1860,7 @@ static void ioapic_configure_entry(struct irq_data *i= rqd) * ioapic chip to verify that. */ if (irqd->chip =3D=3D &ioapic_chip) { - mpd->entry.dest =3D cfg->dest_apicid; + mpd->entry.destid_0_7 =3D cfg->dest_apicid; mpd->entry.vector =3D cfg->vector; } for_each_irq_pin(entry, mpd->irq_2_pin) @@ -1932,7 +1918,7 @@ static int ioapic_irq_get_chip_state(struct irq_data = *irqd, * irrelevant because the IO-APIC treats them as fire and * forget. */ - if (rentry.irr && rentry.trigger) { + if (rentry.irr && rentry.is_level) { *state =3D true; break; } @@ -2057,12 +2043,12 @@ static inline void __init unlock_ExtINT_logic(void) =20 memset(&entry1, 0, sizeof(entry1)); =20 - entry1.dest_mode =3D IOAPIC_DEST_MODE_PHYSICAL; - entry1.mask =3D IOAPIC_UNMASKED; - entry1.dest =3D hard_smp_processor_id(); - entry1.delivery_mode =3D APIC_DELIVERY_MODE_EXTINT; - entry1.polarity =3D entry0.polarity; - entry1.trigger =3D IOAPIC_EDGE; + entry1.dest_mode_logical =3D true; + entry1.masked =3D false; + entry1.destid_0_7 =3D hard_smp_processor_id(); + entry1.delivery_mode =3D APIC_DELIVERY_MODE_EXTINT; + entry1.active_low =3D entry0.active_low; + entry1.is_level =3D false; entry1.vector =3D 0; =20 ioapic_write_entry(apic, pin, entry1); @@ -2937,17 +2923,17 @@ static void mp_setup_entry(struct irq_cfg *cfg, str= uct mp_chip_data *data, struct IO_APIC_route_entry *entry) { memset(entry, 0, sizeof(*entry)); - entry->delivery_mode =3D apic->delivery_mode; - entry->dest_mode =3D apic->dest_mode_logical; - entry->dest =3D cfg->dest_apicid; - entry->vector =3D cfg->vector; - entry->trigger =3D data->is_level; - entry->polarity =3D data->active_low; + entry->delivery_mode =3D apic->delivery_mode; + entry->dest_mode_logical =3D apic->dest_mode_logical; + entry->destid_0_7 =3D cfg->dest_apicid; + entry->vector =3D cfg->vector; + entry->is_level =3D data->is_level; + entry->active_low =3D data->active_low; /* * Mask level triggered irqs. Edge triggered irqs are masked * by the irq core code in case they fire. */ - entry->mask =3D data->is_level; + entry->masked =3D data->is_level; } =20 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index b0e5210e53b2..3d72ec7bbbf8 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3687,11 +3687,11 @@ static void irq_remapping_prepare_irte(struct amd_i= r_data *data, entry =3D info->ioapic.entry; info->ioapic.entry =3D NULL; memset(entry, 0, sizeof(*entry)); - entry->vector =3D index; - entry->trigger =3D info->ioapic.is_level; - entry->polarity =3D info->ioapic.active_low; + entry->vector =3D index; + entry->is_level =3D info->ioapic.is_level; + entry->active_low =3D info->ioapic.active_low; /* Mask level triggered irqs. */ - entry->mask =3D info->ioapic.is_level; + entry->masked =3D info->ioapic.is_level; break; =20 case X86_IRQ_ALLOC_TYPE_HPET: diff --git a/drivers/iommu/hyperv-iommu.c b/drivers/iommu/hyperv-iommu.c index e09e2d734c57..1ab7eb918a5c 100644 --- a/drivers/iommu/hyperv-iommu.c +++ b/drivers/iommu/hyperv-iommu.c @@ -52,7 +52,7 @@ static int hyperv_ir_set_affinity(struct irq_data *data, return ret; =20 entry =3D data->chip_data; - entry->dest =3D cfg->dest_apicid; + entry->destid_0_7 =3D cfg->dest_apicid; entry->vector =3D cfg->vector; send_cleanup_vector(cfg); =20 @@ -125,7 +125,7 @@ static int hyperv_irq_remapping_activate(struct irq_dom= ain *domain, struct irq_cfg *cfg =3D irqd_cfg(irq_data); struct IO_APIC_route_entry *entry =3D irq_data->chip_data; =20 - entry->dest =3D cfg->dest_apicid; + entry->destid_0_7 =3D cfg->dest_apicid; entry->vector =3D cfg->vector; =20 return 0; diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_= remapping.c index 54ca69333445..625bdb9f1627 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1279,8 +1279,8 @@ static void intel_irq_remapping_prepare_irte(struct i= ntel_ir_data *data, struct irq_alloc_info *info, int index, int sub_handle) { - struct IR_IO_APIC_route_entry *entry; struct irte *irte =3D &data->irte_entry; + struct IO_APIC_route_entry *entry; =20 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid); switch (info->type) { @@ -1294,22 +1294,21 @@ static void intel_irq_remapping_prepare_irte(struct= intel_ir_data *data, irte->avail, irte->vector, irte->dest_id, irte->sid, irte->sq, irte->svt); =20 - entry =3D (struct IR_IO_APIC_route_entry *)info->ioapic.entry; + entry =3D info->ioapic.entry; info->ioapic.entry =3D NULL; memset(entry, 0, sizeof(*entry)); - entry->index2 =3D (index >> 15) & 0x1; - entry->zero =3D 0; - entry->format =3D 1; - entry->index =3D (index & 0x7fff); + entry->ir_index_15 =3D !!(index & 0x8000); + entry->ir_format =3D true; + entry->ir_index_0_14 =3D index & 0x7fff; /* * IO-APIC RTE will be configured with virtual vector. * irq handler will do the explicit EOI to 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