From: Vignesh R <vigneshr@ti.com>
To: Tony Lindgren <tony@atomide.com>
Cc: "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4] ARM: dts: dra7: Fix up unaligned access setting for PCIe EP
Date: Fri, 28 Sep 2018 10:58:16 +0530 [thread overview]
Message-ID: <eb3bb7ba-e32d-aa0f-1877-985ab3d6fe4c@ti.com> (raw)
In-Reply-To: <20180926172711.GW5662@atomide.com>
On Wednesday 26 September 2018 10:57 PM, Tony Lindgren wrote:
> * Vignesh R <vigneshr@ti.com> [180924 22:25]:
>> Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
>> PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
>> incorrectly documented in the TRM. In fact, the bit positions are
>> swapped. Update the DT bindings for PCIe EP to reflect the same.
>>
>> Fixes: d23f3839fe97 ("ARM: dts: DRA7: Add pcie1 dt node for EP mode")
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>> ---
>>
>> This patch is split from v3 here:
>> https://lore.kernel.org/patchwork/cover/967020/
>> Patch can be applied standalone and has no dependencies on other patches
>> in v3.
>
> Hmm is this needed for v4.19-rc cycle or can this wait for
> v4.20 merge window?
>
v4.20 should be fine.
--
Regards
Vignesh
next prev parent reply other threads:[~2018-09-28 5:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-25 5:21 [PATCH v4] ARM: dts: dra7: Fix up unaligned access setting for PCIe EP Vignesh R
2018-09-26 17:27 ` Tony Lindgren
2018-09-28 5:28 ` Vignesh R [this message]
2018-09-28 17:26 ` Tony Lindgren
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