From: Maxime Ripard <maxime@cerno.tech>
To: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
Eric Anholt <eric@anholt.net>
Cc: dri-devel@lists.freedesktop.org,
linux-rpi-kernel@lists.infradead.org,
bcm-kernel-feedback-list@broadcom.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Dave Stevenson <dave.stevenson@raspberrypi.com>,
Tim Gover <tim.gover@raspberrypi.com>,
Phil Elwell <phil@raspberrypi.com>,
Maxime Ripard <maxime@cerno.tech>
Subject: [PATCH v2 35/91] drm/vc4: Add support for the BCM2711 HVS5
Date: Fri, 24 Apr 2020 17:34:16 +0200 [thread overview]
Message-ID: <ec5044d3762da564028a54c9fb0c3e0328c3c1e5.1587742492.git-series.maxime@cerno.tech> (raw)
In-Reply-To: <cover.d1e741d37e43e1ba2d2ecd93fc81d42a6df99d14.1587742492.git-series.maxime@cerno.tech>
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
The HVS found in the BCM2711 is slightly different from the previous
generations.
Most notably, the display list layout changes a bit, the LBM doesn't have
the same size and the formats ordering for some formats is swapped.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
drivers/gpu/drm/vc4/vc4_crtc.c | 24 +++-
drivers/gpu/drm/vc4/vc4_drv.h | 4 +-
drivers/gpu/drm/vc4/vc4_hvs.c | 16 ++-
drivers/gpu/drm/vc4/vc4_plane.c | 194 ++++++++++++++++++++++++---------
drivers/gpu/drm/vc4/vc4_regs.h | 67 +++++++++++-
5 files changed, 246 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 1208258ad3b2..591a10ae1950 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -551,6 +551,7 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+ u32 dispctrl;
require_hvs_enabled(dev);
@@ -565,11 +566,24 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
* When feeding the transposer, we should operate in oneshot
* mode.
*/
- HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
- VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
- VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
- SCALER_DISPCTRLX_ENABLE |
- (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
+ dispctrl = SCALER_DISPCTRLX_ENABLE;
+
+ if (!vc4->hvs->hvs5)
+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ SCALER_DISPCTRLX_WIDTH) |
+ VC4_SET_FIELD(mode->vdisplay,
+ SCALER_DISPCTRLX_HEIGHT) |
+ (vc4_state->feed_txp ?
+ SCALER_DISPCTRLX_ONESHOT : 0);
+ else
+ dispctrl |= VC4_SET_FIELD(mode->hdisplay,
+ SCALER5_DISPCTRLX_WIDTH) |
+ VC4_SET_FIELD(mode->vdisplay,
+ SCALER5_DISPCTRLX_HEIGHT) |
+ (vc4_state->feed_txp ?
+ SCALER5_DISPCTRLX_ONESHOT : 0);
+
+ HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), dispctrl);
/* When feeding the transposer block the pixelvalve is unneeded and
* should not be enabled.
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 6024de9ecd35..7da417feff5a 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -332,7 +332,11 @@ struct vc4_hvs {
spinlock_t mm_lock;
struct drm_mm_node mitchell_netravali_filter;
+
struct debugfs_regset32 regset;
+
+ /* HVS version 5 flag, therefore requires updated dlist structures */
+ bool hvs5;
};
struct vc4_plane {
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 5a43659da319..0fe4758de03a 100644
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -230,6 +230,9 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
hvs->pdev = pdev;
+ if (of_device_is_compatible(pdev->dev.of_node, "brcm,bcm2711-hvs"))
+ hvs->hvs5 = true;
+
hvs->regs = vc4_ioremap_regs(pdev, 0);
if (IS_ERR(hvs->regs))
return PTR_ERR(hvs->regs);
@@ -238,7 +241,10 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
hvs->regset.regs = hvs_regs;
hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
- hvs->dlist = hvs->regs + SCALER_DLIST_START;
+ if (!hvs->hvs5)
+ hvs->dlist = hvs->regs + SCALER_DLIST_START;
+ else
+ hvs->dlist = hvs->regs + SCALER5_DLIST_START;
spin_lock_init(&hvs->mm_lock);
@@ -256,7 +262,12 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
* between planes when they don't overlap on the screen, but
* for now we just allocate globally.
*/
- drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
+ if (!hvs->hvs5)
+ /* 96kB */
+ drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
+ else
+ /* 70k words */
+ drm_mm_init(&hvs->lbm_mm, 0, 70 * 2 * 1024);
/* Upload filter kernels. We only have the one for now, so we
* keep it around for the lifetime of the driver.
@@ -341,6 +352,7 @@ static int vc4_hvs_dev_remove(struct platform_device *pdev)
}
static const struct of_device_id vc4_hvs_dt_match[] = {
+ { .compatible = "brcm,bcm2711-hvs" },
{ .compatible = "brcm,bcm2835-hvs" },
{}
};
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 57a73a2e2e5c..1575c05e3106 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -32,45 +32,60 @@ static const struct hvs_format {
u32 drm; /* DRM_FORMAT_* */
u32 hvs; /* HVS_FORMAT_* */
u32 pixel_order;
+ u32 pixel_order_hvs5;
} hvs_formats[] = {
{
- .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_XRGB8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
},
{
- .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_ARGB8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
},
{
- .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_ABGR8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ARGB,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
+ .drm = DRM_FORMAT_XBGR8888,
+ .hvs = HVS_PIXEL_FORMAT_RGBA8888,
.pixel_order = HVS_PIXEL_ORDER_ARGB,
+ .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
+ .drm = DRM_FORMAT_RGB565,
+ .hvs = HVS_PIXEL_FORMAT_RGB565,
.pixel_order = HVS_PIXEL_ORDER_XRGB,
},
{
- .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
+ .drm = DRM_FORMAT_BGR565,
+ .hvs = HVS_PIXEL_FORMAT_RGB565,
.pixel_order = HVS_PIXEL_ORDER_XBGR,
},
{
- .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
+ .drm = DRM_FORMAT_ARGB1555,
+ .hvs = HVS_PIXEL_FORMAT_RGBA5551,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
+ .drm = DRM_FORMAT_XRGB1555,
+ .hvs = HVS_PIXEL_FORMAT_RGBA5551,
.pixel_order = HVS_PIXEL_ORDER_ABGR,
},
{
- .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
+ .drm = DRM_FORMAT_RGB888,
+ .hvs = HVS_PIXEL_FORMAT_RGB888,
.pixel_order = HVS_PIXEL_ORDER_XRGB,
},
{
- .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
+ .drm = DRM_FORMAT_BGR888,
+ .hvs = HVS_PIXEL_FORMAT_RGB888,
.pixel_order = HVS_PIXEL_ORDER_XBGR,
},
{
@@ -781,35 +796,6 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
return -EINVAL;
}
- /* Control word */
- vc4_dlist_write(vc4_state,
- SCALER_CTL0_VALID |
- (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
- (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
- VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
- (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
- (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
- VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
- (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
- VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
- VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
-
- /* Position Word 0: Image Positions and Alpha Value */
- vc4_state->pos0_offset = vc4_state->dlist_count;
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
- VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
- VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
-
- /* Position Word 1: Scaled Image Dimensions. */
- if (!vc4_state->is_unity) {
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(vc4_state->crtc_w,
- SCALER_POS1_SCL_WIDTH) |
- VC4_SET_FIELD(vc4_state->crtc_h,
- SCALER_POS1_SCL_HEIGHT));
- }
-
/* Don't waste cycles mixing with plane alpha if the set alpha
* is opaque or there is no per-pixel alpha information.
* In any case we use the alpha property value as the fixed alpha.
@@ -817,20 +803,120 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
fb->format->has_alpha;
- /* Position Word 2: Source Image Size, Alpha */
- vc4_state->pos2_offset = vc4_state->dlist_count;
- vc4_dlist_write(vc4_state,
- VC4_SET_FIELD(fb->format->has_alpha ?
- SCALER_POS2_ALPHA_MODE_PIPELINE :
- SCALER_POS2_ALPHA_MODE_FIXED,
- SCALER_POS2_ALPHA_MODE) |
- (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
- (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
- VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
- VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
+ if (!vc4->hvs->hvs5) {
+ /* Control word */
+ vc4_dlist_write(vc4_state,
+ SCALER_CTL0_VALID |
+ (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
+ (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
+ VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
+ (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
+ (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
+ VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
+ (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
+ VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
+ VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
+
+ /* Position Word 0: Image Positions and Alpha Value */
+ vc4_state->pos0_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
+ VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
+ VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
+
+ /* Position Word 1: Scaled Image Dimensions. */
+ if (!vc4_state->is_unity) {
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->crtc_w,
+ SCALER_POS1_SCL_WIDTH) |
+ VC4_SET_FIELD(vc4_state->crtc_h,
+ SCALER_POS1_SCL_HEIGHT));
+ }
+
+ /* Position Word 2: Source Image Size, Alpha */
+ vc4_state->pos2_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(fb->format->has_alpha ?
+ SCALER_POS2_ALPHA_MODE_PIPELINE :
+ SCALER_POS2_ALPHA_MODE_FIXED,
+ SCALER_POS2_ALPHA_MODE) |
+ (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
+ (fb->format->has_alpha ?
+ SCALER_POS2_ALPHA_PREMULT : 0) |
+ VC4_SET_FIELD(vc4_state->src_w[0],
+ SCALER_POS2_WIDTH) |
+ VC4_SET_FIELD(vc4_state->src_h[0],
+ SCALER_POS2_HEIGHT));
+
+ /* Position Word 3: Context. Written by the HVS. */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+
+ } else {
+ u32 hvs_pixel_order = format->pixel_order;
- /* Position Word 3: Context. Written by the HVS. */
- vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+ if (format->pixel_order_hvs5)
+ hvs_pixel_order = format->pixel_order_hvs5;
+
+ /* Control word */
+ vc4_dlist_write(vc4_state,
+ SCALER_CTL0_VALID |
+ (hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |
+ (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
+ VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
+ (vc4_state->is_unity ?
+ SCALER5_CTL0_UNITY : 0) |
+ VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
+ VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |
+ SCALER5_CTL0_ALPHA_EXPAND |
+ SCALER5_CTL0_RGB_EXPAND);
+
+ /* Position Word 0: Image Positions and Alpha Value */
+ vc4_state->pos0_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ (rotation & DRM_MODE_REFLECT_Y ?
+ SCALER5_POS0_VFLIP : 0) |
+ VC4_SET_FIELD(vc4_state->crtc_x,
+ SCALER_POS0_START_X) |
+ (rotation & DRM_MODE_REFLECT_X ?
+ SCALER5_POS0_HFLIP : 0) |
+ VC4_SET_FIELD(vc4_state->crtc_y,
+ SCALER5_POS0_START_Y)
+ );
+
+ /* Control Word 2 */
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(state->alpha >> 4,
+ SCALER5_CTL2_ALPHA) |
+ fb->format->has_alpha ?
+ SCALER5_CTL2_ALPHA_PREMULT : 0 |
+ (mix_plane_alpha ?
+ SCALER5_CTL2_ALPHA_MIX : 0) |
+ VC4_SET_FIELD(fb->format->has_alpha ?
+ SCALER5_CTL2_ALPHA_MODE_PIPELINE :
+ SCALER5_CTL2_ALPHA_MODE_FIXED,
+ SCALER5_CTL2_ALPHA_MODE)
+ );
+
+ /* Position Word 1: Scaled Image Dimensions. */
+ if (!vc4_state->is_unity) {
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->crtc_w,
+ SCALER_POS1_SCL_WIDTH) |
+ VC4_SET_FIELD(vc4_state->crtc_h,
+ SCALER_POS1_SCL_HEIGHT));
+ }
+
+ /* Position Word 2: Source Image Size */
+ vc4_state->pos2_offset = vc4_state->dlist_count;
+ vc4_dlist_write(vc4_state,
+ VC4_SET_FIELD(vc4_state->src_w[0],
+ SCALER5_POS2_WIDTH) |
+ VC4_SET_FIELD(vc4_state->src_h[0],
+ SCALER5_POS2_HEIGHT));
+
+ /* Position Word 3: Context. Written by the HVS. */
+ vc4_dlist_write(vc4_state, 0xc0c0c0c0);
+ }
/* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
@@ -1208,6 +1294,10 @@ static bool vc4_format_mod_supported(struct drm_plane *plane,
default:
return false;
}
+ case DRM_FORMAT_RGBX1010102:
+ case DRM_FORMAT_BGRX1010102:
+ case DRM_FORMAT_RGBA1010102:
+ case DRM_FORMAT_BGRA1010102:
case DRM_FORMAT_YUV422:
case DRM_FORMAT_YVU422:
case DRM_FORMAT_YUV420:
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index b5a6b4cdd332..8a51baf681fe 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -328,6 +328,20 @@
# define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
+# define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16)
+# define SCALER5_DISPCTRLX_WIDTH_SHIFT 16
+/* Generates a single frame when VSTART is seen and stops at the last
+ * pixel read from the FIFO.
+ */
+# define SCALER5_DISPCTRLX_ONESHOT BIT(15)
+/* Processes a single context in the dlist and then task switch,
+ * instead of an entire line.
+ */
+# define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13)
+# define SCALER5_DISPCTRLX_ONECTX_SHIFT 13
+# define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0)
+# define SCALER5_DISPCTRLX_HEIGHT_SHIFT 0
+
#define SCALER_DISPBKGND0 0x00000044
# define SCALER_DISPBKGND_AUTOHS BIT(31)
# define SCALER_DISPBKGND_INTERLACE BIT(30)
@@ -461,6 +475,8 @@
#define SCALER_DLIST_START 0x00002000
#define SCALER_DLIST_SIZE 0x00004000
+#define SCALER5_DLIST_START 0x00004000
+
#define VC4_HDMI_CORE_REV 0x000
#define VC4_HDMI_SW_RESET_CONTROL 0x004
@@ -826,6 +842,8 @@ enum hvs_pixel_format {
HVS_PIXEL_FORMAT_PALETTE = 13,
HVS_PIXEL_FORMAT_YUV444_RGB = 14,
HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
+ HVS_PIXEL_FORMAT_RGBA1010102 = 16,
+ HVS_PIXEL_FORMAT_YCBCR_10BIT = 17,
};
/* Note: the LSB is the rightmost character shown. Only valid for
@@ -880,6 +898,10 @@ enum hvs_pixel_format {
#define SCALER_CTL0_RGBA_EXPAND_MSB 2
#define SCALER_CTL0_RGBA_EXPAND_ROUND 3
+#define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
+
+#define SCALER5_CTL0_RGB_EXPAND BIT(11)
+
#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
#define SCALER_CTL0_SCL1_SHIFT 8
@@ -897,10 +919,13 @@ enum hvs_pixel_format {
/* Set to indicate no scaling. */
#define SCALER_CTL0_UNITY BIT(4)
+#define SCALER5_CTL0_UNITY BIT(15)
#define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
#define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
+#define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)
+
#define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
#define SCALER_POS0_FIXED_ALPHA_SHIFT 24
@@ -910,12 +935,48 @@ enum hvs_pixel_format {
#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
#define SCALER_POS0_START_X_SHIFT 0
+#define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16)
+#define SCALER5_POS0_START_Y_SHIFT 16
+
+#define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)
+#define SCALER5_POS0_START_X_SHIFT 0
+
+#define SCALER5_POS0_VFLIP BIT(31)
+#define SCALER5_POS0_HFLIP BIT(15)
+
+#define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
+#define SCALER5_CTL2_ALPHA_MODE_SHIFT 30
+#define SCALER5_CTL2_ALPHA_MODE_PIPELINE 0
+#define SCALER5_CTL2_ALPHA_MODE_FIXED 1
+#define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO 2
+#define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 3
+
+#define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
+
+#define SCALER5_CTL2_ALPHA_MIX BIT(28)
+
+#define SCALER5_CTL2_ALPHA_LOC BIT(25)
+
+#define SCALER5_CTL2_MAP_SEL_MASK VC4_MASK(18, 17)
+#define SCALER5_CTL2_MAP_SEL_SHIFT 17
+
+#define SCALER5_CTL2_GAMMA BIT(16)
+
+#define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4)
+#define SCALER5_CTL2_ALPHA_SHIFT 4
+
#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
#define SCALER_POS1_SCL_HEIGHT_SHIFT 16
#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
#define SCALER_POS1_SCL_WIDTH_SHIFT 0
+#define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16)
+#define SCALER5_POS1_SCL_HEIGHT_SHIFT 16
+
+#define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
+#define SCALER5_POS1_SCL_WIDTH_SHIFT 0
+
#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
#define SCALER_POS2_ALPHA_MODE_SHIFT 30
#define SCALER_POS2_ALPHA_MODE_PIPELINE 0
@@ -931,6 +992,12 @@ enum hvs_pixel_format {
#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
#define SCALER_POS2_WIDTH_SHIFT 0
+#define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16)
+#define SCALER5_POS2_HEIGHT_SHIFT 16
+
+#define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0)
+#define SCALER5_POS2_WIDTH_SHIFT 0
+
/* Color Space Conversion words. Some values are S2.8 signed
* integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
* 0x2: 2, 0x3: -1}
--
git-series 0.9.1
next prev parent reply other threads:[~2020-04-24 15:40 UTC|newest]
Thread overview: 142+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-24 15:33 [PATCH v2 00/91] drm/vc4: Support BCM2711 Display Pipeline Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 01/91] i2c: brcmstb: Allow to compile it on BCM2835 Maxime Ripard
2020-04-24 16:13 ` Wolfram Sang
2020-04-24 17:07 ` Florian Fainelli
2020-04-24 19:04 ` Wolfram Sang
2020-04-26 7:44 ` Wolfram Sang
2020-04-24 15:33 ` [PATCH v2 02/91] dt-bindings: arm: bcm: Convert BCM2835 firmware binding to YAML Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 03/91] dt-bindings: clock: Add a binding for the RPi Firmware clocks Maxime Ripard
2020-05-11 21:47 ` Rob Herring
2020-05-13 8:13 ` Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 04/91] firmware: rpi: Only create clocks device if we don't have a node for it Maxime Ripard
2020-04-27 11:24 ` Nicolas Saenz Julienne
2020-04-28 13:50 ` Maxime Ripard
2020-04-30 16:27 ` Nicolas Saenz Julienne
2020-04-24 15:33 ` [PATCH v2 05/91] clk: bcm: rpi: Allow the driver to be probed by DT Maxime Ripard
2020-04-30 16:19 ` Nicolas Saenz Julienne
2020-04-24 15:33 ` [PATCH v2 06/91] clk: bcm: rpi: Statically init clk_init_data Maxime Ripard
2020-05-27 6:47 ` Stephen Boyd
2020-04-24 15:33 ` [PATCH v2 07/91] clk: bcm: rpi: Use clk_hw_register for pllb_arm Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 08/91] clk: bcm: rpi: Remove global pllb_arm clock pointer Maxime Ripard
2020-05-27 6:48 ` Stephen Boyd
2020-04-24 15:33 ` [PATCH v2 09/91] clk: bcm: rpi: Make sure pllb_arm is removed Maxime Ripard
2020-05-27 6:48 ` Stephen Boyd
2020-04-24 15:33 ` [PATCH v2 10/91] clk: bcm: rpi: Remove pllb_arm_lookup global pointer Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 11/91] clk: bcm: rpi: Switch to clk_hw_register_clkdev Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 12/91] clk: bcm: rpi: Make sure the clkdev lookup is removed Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 13/91] clk: bcm: rpi: Create a data structure for the clocks Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 14/91] clk: bcm: rpi: Add clock id to data Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 15/91] clk: bcm: rpi: Pass the clocks data to the firmware function Maxime Ripard
2020-05-27 6:49 ` Stephen Boyd
2020-04-24 15:33 ` [PATCH v2 16/91] clk: bcm: rpi: Rename is_prepared function Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 17/91] clk: bcm: rpi: Split pllb clock hooks Maxime Ripard
2020-04-24 15:33 ` [PATCH v2 18/91] clk: bcm: rpi: Make the PLLB registration function return a clk_hw Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 19/91] clk: bcm: rpi: Add DT provider for the clocks Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 20/91] clk: bcm: rpi: Discover the firmware clocks Maxime Ripard
2020-05-04 12:05 ` Nicolas Saenz Julienne
2020-05-15 8:19 ` Maxime Ripard
2020-05-21 9:13 ` Nicolas Saenz Julienne
2020-05-27 7:03 ` Stephen Boyd
2020-04-24 15:34 ` [PATCH v2 21/91] ARM: dts: bcm2711: Add firmware clocks node Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 22/91] reset: Move reset-simple header out of drivers/reset Maxime Ripard
2020-05-06 9:26 ` Philipp Zabel
2020-05-13 11:52 ` Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 23/91] reset: simple: Add reset callback Maxime Ripard
2020-05-06 9:26 ` Philipp Zabel
2020-04-24 15:34 ` [PATCH v2 24/91] dt-bindings: clock: Add BCM2711 DVP binding Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 25/91] clk: bcm: Add BCM2711 DVP driver Maxime Ripard
2020-05-27 7:06 ` Stephen Boyd
2020-04-24 15:34 ` [PATCH v2 26/91] ARM: dts: bcm2711: Add HDMI DVP Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 27/91] dt-bindings: display: Convert VC4 bindings to schemas Maxime Ripard
2020-04-27 21:32 ` Rob Herring
2020-04-24 15:34 ` [PATCH v2 28/91] dt-bindings: display: vc4: dpi: Add missing clock-names property Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 29/91] dt-bindings: display: vc4: dsi: Add missing clock properties Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 30/91] dt-bindings: display: vc4: hdmi: Add missing clock-names property Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 31/91] dt-bindings: display: vc4: Document BCM2711 VC5 Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 32/91] drm/vc4: drv: Add include guards Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 33/91] drm/vc4: drv: Support BCM2711 Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 34/91] dt-bindings: display: Add support for the BCM2711 HVS Maxime Ripard
2020-04-24 15:34 ` Maxime Ripard [this message]
2020-04-24 15:34 ` [PATCH v2 36/91] drm/vc4: hvs: Boost the core clock during modeset Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 37/91] drm/vc4: plane: Improve LBM usage Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 38/91] drm/vc4: plane: Move planes creation to its own function Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 39/91] drm/vc4: plane: Move additional planes creation to driver Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 40/91] drm/vc4: plane: Register all the planes at once Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 41/91] drm/vc4: plane: Create overlays for any CRTC Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 42/91] drm/vc4: plane: Create more planes Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 43/91] drm/vc4: crtc: Rename SoC data structures Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 44/91] drm/vc4: crtc: Move crtc state to common header Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 45/91] drm/vc4: crtc: Deal with different number of pixel per clock Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 46/91] drm/vc4: crtc: Use a shared interrupt Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 47/91] drm/vc4: crtc: Turn static const variable into a define Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 48/91] drm/vc4: crtc: Move the cob allocation outside of bind Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 49/91] drm/vc4: crtc: Rename HVS channel to output Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 50/91] drm/vc4: crtc: Use local chan variable Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 51/91] drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 52/91] drm/vc4: crtc: Assign output to channel automatically Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 53/91] drm/vc4: crtc: Add FIFO depth to vc4_crtc_data Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 54/91] drm/vc4: crtc: Add function to compute FIFO level bits Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 55/91] drm/vc4: crtc: Rename HDMI encoder type to HDMI0 Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 56/91] drm/vc4: crtc: Add HDMI1 encoder type Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 57/91] drm/vc4: crtc: Remove redundant call to drm_crtc_enable_color_mgmt Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 58/91] drm/vc4: crtc: Disable color management for HVS5 Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 59/91] dt-bindings: display: vc4: pv: Add BCM2711 pixel valves Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 60/91] drm/vc4: crtc: Add BCM2711 pixelvalves Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 61/91] drm/vc4: hdmi: Use debugfs private field Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 62/91] drm/vc4: hdmi: Move structure to header Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 63/91] drm/vc4: hdmi: rework connectors and encoders Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 64/91] drm/vc4: hdmi: Remove DDC argument to connector_init Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 65/91] drm/vc4: hdmi: Rename hdmi to vc4_hdmi Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 66/91] drm/vc4: hdmi: Move accessors " Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 67/91] drm/vc4: hdmi: Use local vc4_hdmi directly Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 68/91] drm/vc4: hdmi: Add container_of macros for encoders and connectors Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 69/91] drm/vc4: hdmi: Pass vc4_hdmi to CEC code Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 70/91] drm/vc4: hdmi: Remove vc4_dev hdmi pointer Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 71/91] drm/vc4: hdmi: Remove vc4_hdmi_connector Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 72/91] drm/vc4: hdmi: Introduce resource init and variant Maxime Ripard
2020-04-25 21:06 ` Stefan Wahren
2020-04-24 15:34 ` [PATCH v2 73/91] drm/vc4: hdmi: Implement a register layout abstraction Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 74/91] drm/vc4: hdmi: Add reset callback Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 75/91] drm/vc4: hdmi: Add PHY init and disable function Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 76/91] drm/vc4: hdmi: Add PHY RNG enable / " Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 77/91] drm/vc4: hdmi: Add a CSC setup callback Maxime Ripard
2020-04-24 15:34 ` [PATCH v2 78/91] drm/vc4: hdmi: Store the encoder type in the variant structure Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 79/91] drm/vc4: hdmi: Deal with multiple debugfs files Maxime Ripard
2020-04-25 21:26 ` Stefan Wahren
2020-04-28 15:57 ` Maxime Ripard
2020-04-28 16:19 ` Dave Stevenson
2020-04-24 15:35 ` [PATCH v2 80/91] drm/vc4: hdmi: Move CEC init to its own function Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 81/91] drm/vc4: hdmi: Add CEC support flag Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 82/91] drm/vc4: hdmi: Remove unused CEC_CLOCK_DIV define Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 83/91] drm/vc4: hdmi: Rename drm_encoder pointer in mode_valid Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 84/91] drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 85/91] drm/vc4: hdmi: Use reg-names to retrieve the HDMI audio registers Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 86/91] drm/vc4: hdmi: Reset audio infoframe on encoder_enable if previously streaming Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 87/91] drm/vc4: hdmi: Set the b-frame marker to the match ALSA's default Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 88/91] drm/vc4: hdmi: Add audio-related callbacks Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 89/91] drm/vc4: hdmi: Support the BCM2711 HDMI controllers Maxime Ripard
2020-05-07 17:36 ` Stefan Wahren
2020-04-24 15:35 ` [PATCH v2 90/91] dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI controllers bindings Maxime Ripard
2020-05-11 21:50 ` Rob Herring
2020-05-13 8:16 ` Maxime Ripard
2020-04-24 15:35 ` [PATCH v2 91/91] ARM: dts: bcm2711: Enable the display pipeline Maxime Ripard
2020-04-25 20:54 ` Stefan Wahren
2020-04-28 14:11 ` Maxime Ripard
2020-04-27 7:23 ` [PATCH v2 00/91] drm/vc4: Support BCM2711 Display Pipelin Jian-Hong Pan
2020-04-28 16:21 ` Maxime Ripard
2020-05-04 6:35 ` Jian-Hong Pan
2020-05-07 17:21 ` Maxime Ripard
2020-05-08 6:20 ` Jian-Hong Pan
2020-05-11 3:12 ` Jian-Hong Pan
2020-05-25 11:11 ` Maxime Ripard
2020-05-26 10:20 ` Maxime Ripard
2020-05-27 3:49 ` Daniel Drake
2020-05-27 9:13 ` Maxime Ripard
2020-05-27 9:15 ` Daniel Drake
2020-05-28 7:30 ` Maxime Ripard
2020-06-01 7:58 ` Jian-Hong Pan
2020-06-02 11:04 ` Maxime Ripard
2020-06-05 8:44 ` Jian-Hong Pan
2020-06-29 14:21 ` Maxime Ripard
2020-06-30 8:26 ` Jian-Hong Pan
2020-07-03 12:56 ` Maxime Ripard
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