From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52BA2C43467 for ; Thu, 8 Oct 2020 12:55:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E781D207DE for ; Thu, 8 Oct 2020 12:55:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="3hBCcETQ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730153AbgJHMzR (ORCPT ); Thu, 8 Oct 2020 08:55:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729722AbgJHMzR (ORCPT ); Thu, 8 Oct 2020 08:55:17 -0400 Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:8b0:10b:1231::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50502C061755; Thu, 8 Oct 2020 05:55:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=merlin.20170209; h=Mime-Version:Content-Type:References: In-Reply-To:Date:Cc:To:From:Subject:Message-ID:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=aNNcCE0mbpOZLAl8UNG8xrkvYMgkEwtJCWwcUQOMat0=; b=3hBCcETQ3DdLeBpJqqnuGC5xu0 QTxF82DJF+beio/ndQd4cLKOTgWola33+aM/sHFz6S9D5dmZPbeX0ONuWIziE1f9vncdemcOcw8EF wAncHw6DAGZecvKiU1fvLE0YHCG1yGBp6/UvKPa56XABb+syFmCAjAbkdsHyW9Dj11PBq4J50he4p ly5x6lexT4oq165DG2RcupmLOAhu7sCuvJWWtPeFczaAr75FgeZUuAZ5SMer+B4eKcnziNkYTdto5 vUz9M1nDa+O7WsL6thbXaWpMaekhm//m4x7P1uA43qZRwn0bBvD2eyc6q+nbrj+uA9LmPb1w1lbxg IkElzxbw==; Received: from [54.239.6.186] (helo=freeip.amazon.com) by merlin.infradead.org with esmtpsa (Exim 4.92.3 #3 (Red Hat Linux)) id 1kQVRw-0006EV-As; Thu, 08 Oct 2020 12:55:12 +0000 Message-ID: Subject: Re: [PATCH 5/5] x86/kvm: Add KVM_FEATURE_MSI_EXT_DEST_ID From: David Woodhouse To: Thomas Gleixner , x86@kernel.org Cc: kvm , Paolo Bonzini , linux-kernel Date: Thu, 08 Oct 2020 13:55:10 +0100 In-Reply-To: <87blhcx6qz.fsf@nanos.tec.linutronix.de> References: <803bb6b2212e65c568c84ff6882c2aa8a0ee03d5.camel@infradead.org> <20201007122046.1113577-1-dwmw2@infradead.org> <20201007122046.1113577-5-dwmw2@infradead.org> <87blhcx6qz.fsf@nanos.tec.linutronix.de> Content-Type: multipart/signed; micalg="sha-256"; protocol="application/x-pkcs7-signature"; boundary="=-erlCzoHY6Q60DDG0SDRX" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 Mime-Version: 1.0 X-SRS-Rewrite: SMTP reverse-path rewritten from by merlin.infradead.org. See http://www.infradead.org/rpr.html Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-erlCzoHY6Q60DDG0SDRX Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 2020-10-08 at 14:05 +0200, Thomas Gleixner wrote: > Why MSI_EXT_DEST_ID? It's enabling that for MSI and IO/APIC. The > underlying mechanism might be the same, but APIC_EXT_DEST_ID is more > general and then you might also make the explanation of that bit > match the changelog. It's enabling it for *everything* that generates MSI cycles =E2=80=94 which includes IOAPIC, HPET, and MSI-capable PCI devices. Hell, and anything else which feels like generating a physical address cycle to 0xFEExxxxx addresses. Again, the IOAPIC is just a device for turning pin-based interrupts into MSIs. Bits 19-4 of the address it writes to are taken directly from bits 63-48 of the IOAPIC RTE. There's complexity elsewhere but for *those* bits, It just uses the bits it's given, just like a PCI device or an HPET would.=20 When I implemented this in qemu I didn't even *touch* the IOAPIC support; it doesn't affect the IOAPIC at all, just like it doesn't affect the HPET or any of the MSI-capable PCI devices that qemu emulates. They just put the bits on the bus that they're told to, when they want to generate an interrupt. This feature is an MSI feature. Not an HPET feature. Not a PCI feature. Not an IOAPIC feature. The fact that a *Linux* guest has special-case knowledge in its IOAPIC driver that duplicates what the MSI message composition does, is not a good justification for naming the feature bit bizarrely. In fact I'm really tempted to make Linux's io_apic.c just use irq_chip_compose_msi_msg() and swizzle the bits out of the message identically for IR and non-IR alike (modulo the pin hack), and delete the IR_IO_APIC_route_entry struct completely.=20 That also completely removes the ext_dest_id trick from visibility in io_apic.c. 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