From: tip-bot for Linus Torvalds <torvalds@linux-foundation.org>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, wei.chong.tan@intel.com,
hpa@zytor.com, mingo@redhat.com, torvalds@linux-foundation.org,
tglx@linutronix.de, mingo@elte.hu
Subject: [tip:x86/urgent] x86: Fix serialization in pit_expect_msb()
Date: Mon, 10 Aug 2009 09:06:40 GMT [thread overview]
Message-ID: <tip-672f3c902d13ba6d4a8bc4bb92fb187ccd906908@git.kernel.org> (raw)
In-Reply-To: <B28277FD4E0F9247A3D55704C440A140D5D683F3@pgsmsx504.gar.corp.intel.com>
Commit-ID: 672f3c902d13ba6d4a8bc4bb92fb187ccd906908
Gitweb: http://git.kernel.org/tip/672f3c902d13ba6d4a8bc4bb92fb187ccd906908
Author: Linus Torvalds <torvalds@linux-foundation.org>
AuthorDate: Fri, 31 Jul 2009 12:45:41 -0700
Committer: Ingo Molnar <mingo@elte.hu>
CommitDate: Mon, 10 Aug 2009 11:03:51 +0200
x86: Fix serialization in pit_expect_msb()
Wei Chong Tan reported a fast-PIT-calibration corner-case:
| pit_expect_msb() is vulnerable to SMI disturbance corner case
| in some platforms which causes /proc/cpuinfo to show wrong
| CPU MHz value when quick_pit_calibrate() jumps to success
| section.
I think that the real issue isn't even an SMI - but the fact
that in the very last iteration of the loop, there's no
serializing instruction _after_ the last 'rdtsc'. So even in
the absense of SMI's, we do have a situation where the cycle
counter was read without proper serialization.
The last check should be done outside the outer loop, since
_inside_ the outer loop, we'll be testing that the PIT has
the right MSB value has the right value in the next iteration.
So only the _last_ iteration is special, because that's the one
that will not check the PIT MSB value any more, and because the
final 'get_cycles()' isn't serialized.
In other words:
- I'd like to move the PIT MSB check to after the last
iteration, rather than in every iteration
- I think we should comment on the fact that it's also a
serializing instruction and so 'fences in' the TSC read.
Here's a suggested replacement.
Reported-by: "Tan, Wei Chong" <wei.chong.tan@intel.com>
Tested-by: "Tan, Wei Chong" <wei.chong.tan@intel.com>
LKML-Reference: <B28277FD4E0F9247A3D55704C440A140D5D683F3@pgsmsx504.gar.corp.intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/tsc.c | 29 ++++++++++++++++++++++-------
1 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 6e1a368..71f4368 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -275,15 +275,20 @@ static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
* use the TSC value at the transitions to calculate a pretty
* good value for the TSC frequencty.
*/
+static inline int pit_verify_msb(unsigned char val)
+{
+ /* Ignore LSB */
+ inb(0x42);
+ return inb(0x42) == val;
+}
+
static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
{
int count;
u64 tsc = 0;
for (count = 0; count < 50000; count++) {
- /* Ignore LSB */
- inb(0x42);
- if (inb(0x42) != val)
+ if (!pit_verify_msb(val))
break;
tsc = get_cycles();
}
@@ -336,8 +341,7 @@ static unsigned long quick_pit_calibrate(void)
* to do that is to just read back the 16-bit counter
* once from the PIT.
*/
- inb(0x42);
- inb(0x42);
+ pit_verify_msb(0);
if (pit_expect_msb(0xff, &tsc, &d1)) {
for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
@@ -348,8 +352,19 @@ static unsigned long quick_pit_calibrate(void)
* Iterate until the error is less than 500 ppm
*/
delta -= tsc;
- if (d1+d2 < delta >> 11)
- goto success;
+ if (d1+d2 >= delta >> 11)
+ continue;
+
+ /*
+ * Check the PIT one more time to verify that
+ * all TSC reads were stable wrt the PIT.
+ *
+ * This also guarantees serialization of the
+ * last cycle read ('d2') in pit_expect_msb.
+ */
+ if (!pit_verify_msb(0xfe - i))
+ break;
+ goto success;
}
}
printk("Fast TSC calibration failed\n");
next prev parent reply other threads:[~2009-08-10 9:07 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-07-31 18:13 [GIT PULL] Additional x86 fixes for 2.6.31-rc5 H. Peter Anvin
2009-07-31 19:45 ` Linus Torvalds
2009-07-31 19:57 ` Ingo Molnar
2009-08-01 19:28 ` Linus Torvalds
2009-08-01 19:38 ` H. Peter Anvin
2009-08-01 22:04 ` Linus Torvalds
2009-08-01 22:35 ` H. Peter Anvin
2009-08-02 1:20 ` Paul Mackerras
2009-08-02 3:52 ` H. Peter Anvin
2009-08-03 1:01 ` Tejun Heo
2009-08-03 1:14 ` Linus Torvalds
2009-08-03 1:49 ` Tejun Heo
2009-08-03 2:14 ` Linus Torvalds
2009-08-03 5:08 ` [PATCH 1/3] x86: Add 'percpu_read_stable()' interface for cacheable accesses Tejun Heo
2009-08-03 5:13 ` H. Peter Anvin
2009-08-03 5:18 ` Tejun Heo
2009-08-03 6:04 ` Ingo Molnar
2009-08-03 6:08 ` H. Peter Anvin
2009-08-03 6:16 ` Ingo Molnar
2009-08-03 7:00 ` Ingo Molnar
2009-08-03 15:13 ` [PATCH 1/3 UPDATED] x86, percpu: " Tejun Heo
2009-08-03 5:10 ` [PATCH 2/3] x86,percpu: fix DECLARE/DEFINE_PER_CPU_PAGE_ALIGNED() Tejun Heo
2009-08-03 5:12 ` [PATCH 3/3] x86: collect hot percpu variables into one cacheline Tejun Heo
2009-08-05 7:34 ` [GIT PULL] Additional x86 fixes for 2.6.31-rc5 Tan, Wei Chong
2009-08-05 8:06 ` Ingo Molnar
2009-08-10 0:42 ` Tan, Wei Chong
2009-08-10 9:05 ` Ingo Molnar
2009-08-10 15:32 ` Linus Torvalds
2009-08-10 9:06 ` tip-bot for Linus Torvalds [this message]
2009-08-10 18:01 ` [tip:x86/urgent] x86: Fix serialization in pit_expect_msb() tip-bot for Linus Torvalds
2009-08-05 23:10 ` [GIT PULL] Additional x86 fixes for 2.6.31-rc5 Tan, Wei Chong
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