From: Dongdong Liu <liudongdong3@huawei.com>
To: <helgaas@kernel.org>, <hch@infradead.org>, <kw@linux.com>,
<linux-pci@vger.kernel.org>, <rajur@chelsio.com>,
<hverkuil-cisco@xs4all.nl>
Cc: <linux-media@vger.kernel.org>, <netdev@vger.kernel.org>
Subject: [RESEND PATCH V3 6/6] PCI: Enable 10-Bit tag support for PCIe RP devices
Date: Sun, 13 Jun 2021 17:29:15 +0800 [thread overview]
Message-ID: <1623576555-40338-7-git-send-email-liudongdong3@huawei.com> (raw)
In-Reply-To: <1623576555-40338-1-git-send-email-liudongdong3@huawei.com>
PCIe spec 5.0r1.0 section 2.2.6.2 implementation note, In configurations
where a Requester with 10-Bit Tag Requester capability needs to target
multiple Completers, one needs to ensure that the Requester sends 10-Bit
Tag Requests only to Completers that have 10-Bit Tag Completer capability.
So we enable 10-Bit Tag Requester for root port only when the devices
under the root port support 10-Bit Tag Completer.
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
---
drivers/pci/pcie/portdrv_pci.c | 75 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c
index c7ff1ee..baf413f 100644
--- a/drivers/pci/pcie/portdrv_pci.c
+++ b/drivers/pci/pcie/portdrv_pci.c
@@ -90,6 +90,78 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = {
#define PCIE_PORTDRV_PM_OPS NULL
#endif /* !PM */
+static int pci_10bit_tag_comp_support(struct pci_dev *dev, void *data)
+{
+ u8 *support = data;
+
+ if (*support == 0)
+ return 0;
+
+ if (!pci_is_pcie(dev)) {
+ *support = 0;
+ return 0;
+ }
+
+ /*
+ * PCIe spec 5.0r1.0 section 2.2.6.2 implementation note.
+ * For configurations where a Requester with 10-Bit Tag Requester
+ * capability targets Completers where some do and some do not have
+ * 10-Bit Tag Completer capability, how the Requester determines which
+ * NPRs include 10-Bit Tags is outside the scope of this specification.
+ * So we do not consider hotplug scenario.
+ */
+ if (dev->is_hotplug_bridge) {
+ *support = 0;
+ return 0;
+ }
+
+ if (!(dev->pcie_devcap2 & PCI_EXP_DEVCAP2_10BIT_TAG_COMP)) {
+ *support = 0;
+ return 0;
+ }
+
+ return 0;
+}
+
+static void pci_configure_rp_10bit_tag(struct pci_dev *dev)
+{
+ u8 support = 1;
+ struct pci_dev *pchild;
+
+ if (dev->subordinate == NULL)
+ return;
+
+ /* If no devices under the root port, no need to enable 10-Bit Tag. */
+ pchild = list_first_entry_or_null(&dev->subordinate->devices,
+ struct pci_dev, bus_list);
+ if (pchild == NULL)
+ return;
+
+ pci_10bit_tag_comp_support(dev, &support);
+ if (!support)
+ return;
+
+ /*
+ * PCIe spec 5.0r1.0 section 2.2.6.2 implementation note.
+ * In configurations where a Requester with 10-Bit Tag Requester
+ * capability needs to target multiple Completers, one needs to ensure
+ * that the Requester sends 10-Bit Tag Requests only to Completers
+ * that have 10-Bit Tag Completer capability. So we enable 10-Bit Tag
+ * Requester for root port only when the devices under the root port
+ * support 10-Bit Tag Completer.
+ */
+ pci_walk_bus(dev->subordinate, pci_10bit_tag_comp_support, &support);
+ if (!support)
+ return;
+
+ if (!(dev->pcie_devcap2 & PCI_EXP_DEVCAP2_10BIT_TAG_REQ))
+ return;
+
+ pci_dbg(dev, "enabling 10-Bit Tag Requester\n");
+ pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
+ PCI_EXP_DEVCTL2_10BIT_TAG_REQ_EN);
+}
+
/*
* pcie_portdrv_probe - Probe PCI-Express port devices
* @dev: PCI-Express port device being probed
@@ -111,6 +183,9 @@ static int pcie_portdrv_probe(struct pci_dev *dev,
(type != PCI_EXP_TYPE_RC_EC)))
return -ENODEV;
+ if (type == PCI_EXP_TYPE_ROOT_PORT)
+ pci_configure_rp_10bit_tag(dev);
+
if (type == PCI_EXP_TYPE_RC_EC)
pcie_link_rcec(dev);
--
2.7.4
next prev parent reply other threads:[~2021-06-13 9:30 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-13 9:29 [RESEND PATCH V3 0/6] PCI: Enable 10-Bit tag support for PCIe devices Dongdong Liu
2021-06-13 9:29 ` [RESEND PATCH V3 1/6] PCI: Use cached Device Capabilities Register Dongdong Liu
2021-06-14 5:42 ` Christoph Hellwig
2021-06-15 3:03 ` Dongdong Liu
2021-06-18 14:51 ` kernel test robot
2021-06-21 7:18 ` Dongdong Liu
2021-06-13 9:29 ` [RESEND PATCH V3 2/6] PCI: Use cached Device Capabilities 2 Register Dongdong Liu
2021-06-14 5:49 ` Christoph Hellwig
2021-06-15 3:04 ` Dongdong Liu
2021-06-13 9:29 ` [RESEND PATCH V3 3/6] PCI: Add 10-Bit Tag register definitions Dongdong Liu
2021-06-14 5:50 ` Christoph Hellwig
2021-06-13 9:29 ` [RESEND PATCH V3 4/6] PCI: Enable 10-Bit tag support for PCIe Endpoint devices Dongdong Liu
2021-06-14 5:54 ` Christoph Hellwig
2021-06-15 3:07 ` Dongdong Liu
2021-06-13 9:29 ` [RESEND PATCH V3 5/6] PCI/IOV: Enable 10-Bit tag support for PCIe VF devices Dongdong Liu
2021-06-14 5:55 ` Christoph Hellwig
2021-06-13 9:29 ` Dongdong Liu [this message]
2021-06-14 5:57 ` [RESEND PATCH V3 6/6] PCI: Enable 10-Bit tag support for PCIe RP devices Christoph Hellwig
2021-06-15 3:08 ` Dongdong Liu
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