From: "Marek Behún" <marek.behun@nic.cz>
To: Andrew Lunn <andrew@lunn.ch>
Cc: netdev@vger.kernel.org, Heiner Kallweit <hkallweit1@gmail.com>,
Sebastian Reichel <sebastian.reichel@collabora.co.uk>,
Vivien Didelot <vivien.didelot@gmail.com>,
Florian Fainelli <f.fainelli@gmail.com>,
"David S . Miller" <davem@davemloft.net>
Subject: Re: [PATCH net-next 1/2] net: dsa: mv88e6xxx: fix RGMII-ID port setup
Date: Tue, 13 Aug 2019 17:44:16 +0200 [thread overview]
Message-ID: <20190813174416.5c57b08f@dellmb.labs.office.nic.cz> (raw)
In-Reply-To: <20190811165108.GG14290@lunn.ch>
Hi Andrew,
> We should read the switch registers. I think you can set the defaults
> using strapping pins. And in general, the driver always reads state
> from the hardware rather than caching it.
hmm. The cmode is cached for each port, though. For example
mv88e6390x_port_set_cmode compares the new requested value with the
cached one and doesn't do anything if they are equal.
If mv88e6xxx_port_setup_mac can be called once per second by phylink as
you say, do we really want to read the value via MDIO every time? We
already have cmode cached (read from registers at mv88e6xxx_setup, and
then changed when cmode change is requested). From cmode we can already
differentiate mode in the terms of phy_interface_t, unless it is RGMII,
in which case we would have to read RX/TX timing.
Marek
next prev parent reply other threads:[~2019-08-13 15:44 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-11 15:08 [PATCH net-next 1/2] net: dsa: mv88e6xxx: fix RGMII-ID port setup Marek Behún
2019-08-11 15:08 ` [PATCH net-next 2/2] net: fixed_phy: set is_gigabit_capable member when needed Marek Behún
2019-08-11 15:40 ` Andrew Lunn
2019-08-11 16:08 ` Marek Behun
2019-08-11 16:59 ` Heiner Kallweit
2019-08-11 15:31 ` [PATCH net-next 1/2] net: dsa: mv88e6xxx: fix RGMII-ID port setup Andrew Lunn
2019-08-11 16:14 ` Marek Behun
2019-08-11 16:51 ` Andrew Lunn
2019-08-13 15:44 ` Marek Behún [this message]
2019-08-13 15:51 ` Marek Behún
2019-08-13 15:52 ` Andrew Lunn
2019-08-12 9:23 ` Sergei Shtylyov
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