From: Andi Kleen <andi@firstfloor.org>
To: Or Gerlitz <gerlitz.or@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Brendan Gregg <bgregg@netflix.com>,
Linux Netdev List <netdev@vger.kernel.org>
Subject: Re: perf measure for stalled cycles per instruction on newer Intel processors
Date: Thu, 15 Oct 2020 11:33:53 -0700 [thread overview]
Message-ID: <20201015183352.o4zmciukdrdvvdj4@two.firstfloor.org> (raw)
In-Reply-To: <CAJ3xEMiOtDe5OeC8oT2NyVu5BEmH_eLgAAH4voLqejWgsvG4xQ@mail.gmail.com>
On Thu, Oct 15, 2020 at 05:53:40PM +0300, Or Gerlitz wrote:
> Hi,
>
> Earlier Intel processors (e.g E5-2650) support the more of classical
> two stall events (for backend and frontend [1]) and then perf shows
> the nice measure of stalled cycles per instruction - e.g here where we
> have IPC of 0.91 and CSPI (see [2]) of 0.68:
Don't use it. It's misleading on a out-of-order CPU because you don't
know if it's actually limiting anything.
If you want useful bottleneck data use --topdown.
-Andi
next prev parent reply other threads:[~2020-10-15 18:40 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-15 14:53 perf measure for stalled cycles per instruction on newer Intel processors Or Gerlitz
2020-10-15 18:33 ` Andi Kleen [this message]
2020-10-18 17:42 ` Or Gerlitz
2020-10-19 1:00 ` Andi Kleen
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