From: "Marek Behún" <kabel@kernel.org>
To: netdev@vger.kernel.org, Russell King <rmk+kernel@armlinux.org.uk>,
Andrew Lunn <andrew@lunn.ch>
Cc: "David S . Miller" <davem@davemloft.net>,
kuba@kernel.org, "Marek Behún" <kabel@kernel.org>
Subject: [PATCH net-next v4 01/16] net: phy: marvell10g: rename register
Date: Wed, 7 Apr 2021 22:22:39 +0200 [thread overview]
Message-ID: <20210407202254.29417-2-kabel@kernel.org> (raw)
In-Reply-To: <20210407202254.29417-1-kabel@kernel.org>
The MV_V2_PORT_MAC_TYPE_* is part of the CTRL register. Rename to
MV_V2_PORT_CTRL_MACTYPE_*.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/phy/marvell10g.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 74b64e52ffa2..9b514124af0d 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -80,8 +80,8 @@ enum {
MV_V2_PORT_CTRL = 0xf001,
MV_V2_PORT_CTRL_SWRST = BIT(15),
MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
- MV_V2_PORT_MAC_TYPE_MASK = 0x7,
- MV_V2_PORT_MAC_TYPE_RATE_MATCH = 0x6,
+ MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7,
+ MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
/* Temperature control/read registers (88X3310 only) */
MV_V2_TEMP_CTRL = 0xf08a,
MV_V2_TEMP_CTRL_MASK = 0xc000,
@@ -477,8 +477,8 @@ static int mv3310_config_init(struct phy_device *phydev)
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
if (val < 0)
return val;
- priv->rate_match = ((val & MV_V2_PORT_MAC_TYPE_MASK) ==
- MV_V2_PORT_MAC_TYPE_RATE_MATCH);
+ priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) ==
+ MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH);
/* Enable EDPD mode - saving 600mW */
return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
--
2.26.2
next prev parent reply other threads:[~2021-04-07 20:24 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-07 20:22 [PATCH net-next v4 00/16] net: phy: marvell10g updates Marek Behún
2021-04-07 20:22 ` Marek Behún [this message]
2021-04-07 20:22 ` [PATCH net-next v4 02/16] net: phy: marvell10g: fix typo Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 03/16] net: phy: marvell10g: allow 5gbase-r and usxgmii Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 04/16] net: phy: marvell10g: indicate 88X33x0 only port control registers Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 05/16] net: phy: marvell10g: add all MACTYPE definitions for 88X33x0 Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 06/16] net: phy: marvell10g: add MACTYPE definitions for 88E21xx Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 07/16] net: phy: marvell10g: support all rate matching modes Marek Behún
2021-04-07 23:03 ` Andrew Lunn
2021-04-07 20:22 ` [PATCH net-next v4 08/16] net: phy: marvell10g: check for correct supported interface mode Marek Behún
2021-04-07 23:05 ` Andrew Lunn
2021-04-07 20:22 ` [PATCH net-next v4 09/16] net: phy: marvell10g: store temperature read method in chip strucutre Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 10/16] net: phy: marvell10g: support other MACTYPEs Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 11/16] net: phy: marvell10g: add separate structure for 88X3340 Marek Behún
2021-04-07 23:09 ` Andrew Lunn
2021-07-10 16:12 ` Matteo Croce
2021-07-11 13:09 ` Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 12/16] net: phy: marvell10g: fix driver name for mv88e2110 Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 13/16] net: phy: add constants for 2.5G and 5G speed in PCS speed register Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 14/16] net: phy: marvell10g: differentiate 88E2110 vs 88E2111 Marek Behún
2021-04-07 23:10 ` Andrew Lunn
2021-04-07 20:22 ` [PATCH net-next v4 15/16] net: phy: marvell10g: change module description Marek Behún
2021-04-07 20:22 ` [PATCH net-next v4 16/16] MAINTAINERS: add myself as maintainer of marvell10g driver Marek Behún
2021-04-08 20:20 ` [PATCH net-next v4 00/16] net: phy: marvell10g updates patchwork-bot+netdevbpf
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