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From: "Marek Behún" <marek.behun@nic.cz>
To: Michal Smulski <msmulski2@gmail.com>
Cc: andrew@lunn.ch, f.fainelli@gmail.com, olteanv@gmail.com,
	netdev@vger.kernel.org, Michal Smulski <michal.smulski@ooma.com>
Subject: Re: [PATCH net-next v2] net: dsa: mv88e6xxx: implement USXGMII mode for mv88e6393x
Date: Sun, 28 May 2023 11:25:22 +0200	[thread overview]
Message-ID: <20230528092522.47enrnrslgflovmx@kandell> (raw)
In-Reply-To: <20230527172024.9154-1-michal.smulski@ooma.com>

You need also to implement serdes_pcs_get_state for USXGMII.

Preferably by adding USXGMII relevant register constants into
include/uapi/linux/mii.h, and using them to parse state register.

Marek

On Sat, May 27, 2023 at 10:20:24AM -0700, Michal Smulski wrote:
> Enable USXGMII mode for mv88e6393x chips. Tested on Marvell 88E6191X.
> 
> Signed-off-by: Michal Smulski <michal.smulski@ooma.com>
> ---
>  drivers/net/dsa/mv88e6xxx/chip.c   |  3 +--
>  drivers/net/dsa/mv88e6xxx/port.c   |  3 +++
>  drivers/net/dsa/mv88e6xxx/serdes.c | 10 ++++++++--
>  3 files changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
> index 5bbe95fa951c..71cee154622f 100644
> --- a/drivers/net/dsa/mv88e6xxx/chip.c
> +++ b/drivers/net/dsa/mv88e6xxx/chip.c
> @@ -806,8 +806,7 @@ static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
>  			__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
>  			__set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
>  			__set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
> -			/* FIXME: USXGMII is not supported yet */
> -			/* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */
> +			__set_bit(PHY_INTERFACE_MODE_USXGMII, supported);
>  
>  			config->mac_capabilities |= MAC_2500FD | MAC_5000FD |
>  				MAC_10000FD;
> diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
> index f79cf716c541..8daeeeb66880 100644
> --- a/drivers/net/dsa/mv88e6xxx/port.c
> +++ b/drivers/net/dsa/mv88e6xxx/port.c
> @@ -554,6 +554,9 @@ static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
>  	case PHY_INTERFACE_MODE_10GBASER:
>  		cmode = MV88E6393X_PORT_STS_CMODE_10GBASER;
>  		break;
> +	case PHY_INTERFACE_MODE_USXGMII:
> +		cmode = MV88E6393X_PORT_STS_CMODE_USXGMII;
> +		break;
>  	default:
>  		cmode = 0;
>  	}
> diff --git a/drivers/net/dsa/mv88e6xxx/serdes.c b/drivers/net/dsa/mv88e6xxx/serdes.c
> index 72faec8f44dc..ae051d383c7e 100644
> --- a/drivers/net/dsa/mv88e6xxx/serdes.c
> +++ b/drivers/net/dsa/mv88e6xxx/serdes.c
> @@ -683,7 +683,8 @@ int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port)
>  	    cmode == MV88E6XXX_PORT_STS_CMODE_SGMII ||
>  	    cmode == MV88E6XXX_PORT_STS_CMODE_2500BASEX ||
>  	    cmode == MV88E6393X_PORT_STS_CMODE_5GBASER ||
> -	    cmode == MV88E6393X_PORT_STS_CMODE_10GBASER)
> +	    cmode == MV88E6393X_PORT_STS_CMODE_10GBASER ||
> +	    cmode == MV88E6393X_PORT_STS_CMODE_USXGMII)
>  		lane = port;
>  
>  	return lane;
> @@ -1018,6 +1019,7 @@ int mv88e6393x_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
>  							    state);
>  	case PHY_INTERFACE_MODE_5GBASER:
>  	case PHY_INTERFACE_MODE_10GBASER:
> +	case PHY_INTERFACE_MODE_USXGMII:
>  		return mv88e6393x_serdes_pcs_get_state_10g(chip, port, lane,
>  							   state);
>  
> @@ -1173,6 +1175,7 @@ int mv88e6393x_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port,
>  		return mv88e6390_serdes_irq_enable_sgmii(chip, lane, enable);
>  	case MV88E6393X_PORT_STS_CMODE_5GBASER:
>  	case MV88E6393X_PORT_STS_CMODE_10GBASER:
> +	case MV88E6393X_PORT_STS_CMODE_USXGMII:
>  		return mv88e6393x_serdes_irq_enable_10g(chip, lane, enable);
>  	}
>  
> @@ -1213,6 +1216,7 @@ irqreturn_t mv88e6393x_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
>  		break;
>  	case MV88E6393X_PORT_STS_CMODE_5GBASER:
>  	case MV88E6393X_PORT_STS_CMODE_10GBASER:
> +	case MV88E6393X_PORT_STS_CMODE_USXGMII:
>  		err = mv88e6393x_serdes_irq_status_10g(chip, lane, &status);
>  		if (err)
>  			return err;
> @@ -1477,7 +1481,8 @@ static int mv88e6393x_serdes_erratum_5_2(struct mv88e6xxx_chip *chip, int lane,
>  	 * to SERDES operating in 10G mode. These registers only apply to 10G
>  	 * operation and have no effect on other speeds.
>  	 */
> -	if (cmode != MV88E6393X_PORT_STS_CMODE_10GBASER)
> +	if (cmode != MV88E6393X_PORT_STS_CMODE_10GBASER &&
> +	    cmode != MV88E6393X_PORT_STS_CMODE_USXGMII)
>  		return 0;
>  
>  	for (i = 0; i < ARRAY_SIZE(fixes); ++i) {
> @@ -1582,6 +1587,7 @@ int mv88e6393x_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
>  		break;
>  	case MV88E6393X_PORT_STS_CMODE_5GBASER:
>  	case MV88E6393X_PORT_STS_CMODE_10GBASER:
> +	case MV88E6393X_PORT_STS_CMODE_USXGMII:
>  		err = mv88e6390_serdes_power_10g(chip, lane, on);
>  		break;
>  	default:
> -- 
> 2.34.1
> 
> 

  reply	other threads:[~2023-05-28  9:31 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-27 17:20 [PATCH net-next v2] net: dsa: mv88e6xxx: implement USXGMII mode for mv88e6393x Michal Smulski
2023-05-28  9:25 ` Marek Behún [this message]
2023-05-29 15:11   ` Andrew Lunn
2023-05-29 17:23     ` Michal Smulski
2023-05-30 13:54       ` Marek Behún
2023-05-31  5:54         ` Michal Smulski

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