From: Diogo Ivo <diogo.ivo@siemens.com>
To: danishanwar@ti.com, rogerq@kernel.org, davem@davemloft.net,
edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
netdev@vger.kernel.org, devicetree@vger.kernel.org
Cc: Diogo Ivo <diogo.ivo@siemens.com>, Jan Kiszka <jan.kiszka@siemens.com>
Subject: [PATCH v2 1/8] dt-bindings: net: Add support for AM65x SR1.0 in ICSSG
Date: Wed, 17 Jan 2024 16:14:55 +0000 [thread overview]
Message-ID: <20240117161602.153233-2-diogo.ivo@siemens.com> (raw)
In-Reply-To: <20240117161602.153233-1-diogo.ivo@siemens.com>
Silicon Revision 1.0 of the AM65x came with a slightly different ICSSG
support: Only 2 PRUs per slice are available and instead 2 additional
DMA channels are used for management purposes. We have no restrictions
on specified PRUs, but the DMA channels need to be adjusted.
Co-developed-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Diogo Ivo <diogo.ivo@siemens.com>
---
Changes in v2:
- Removed explicit reference to SR2.0
- Moved sr1 to the SoC name
- Expand dma-names list and adjust min/maxItems depending on SR1.0/2.0
.../bindings/net/ti,icssg-prueth.yaml | 29 ++++++++++++++++---
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml
index 229c8f32019f..59a3292191d9 100644
--- a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml
+++ b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml
@@ -19,8 +19,9 @@ allOf:
properties:
compatible:
enum:
- - ti,am642-icssg-prueth # for AM64x SoC family
- - ti,am654-icssg-prueth # for AM65x SoC family
+ - ti,am642-icssg-prueth # for AM64x SoC family
+ - ti,am654-icssg-prueth # for AM65x SoC family
+ - ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0
sram:
$ref: /schemas/types.yaml#/definitions/phandle
@@ -28,8 +29,7 @@ properties:
phandle to MSMC SRAM node
dmas:
- maxItems: 10
-
+ minItems: 10
dma-names:
items:
- const: tx0-0
@@ -42,6 +42,8 @@ properties:
- const: tx1-3
- const: rx0
- const: rx1
+ - const: rxmgm0
+ - const: rxmgm1
ti,mii-g-rt:
$ref: /schemas/types.yaml#/definitions/phandle
@@ -132,6 +134,25 @@ required:
- interrupts
- interrupt-names
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,am654-sr1-icssg-prueth
+ then:
+ properties:
+ dmas:
+ minItems: 12
+ dma-names:
+ minItems: 12
+ else:
+ properties:
+ dmas:
+ maxItems: 10
+ dma-names:
+ maxItems: 10
+
unevaluatedProperties: false
examples:
--
2.43.0
next prev parent reply other threads:[~2024-01-17 16:16 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-17 16:14 [PATCH v2 0/8] Add support for ICSSG-based Ethernet on SR1.0 devices Diogo Ivo
2024-01-17 16:14 ` Diogo Ivo [this message]
2024-01-17 17:35 ` [PATCH v2 1/8] dt-bindings: net: Add support for AM65x SR1.0 in ICSSG Rob Herring
2024-01-17 16:14 ` [PATCH v2 3/8] net: ti: icssg-prueth: add SR1.0-specific configuration bits Diogo Ivo
2024-01-17 16:14 ` [PATCH v2 4/8] net: ti: icssg-classifier: Add support for SR1.0 Diogo Ivo
2024-01-17 20:48 ` Andrew Lunn
2024-01-17 16:14 ` [PATCH v2 5/8] net: ti: icssg-config: Add SR1.0 configuration functions Diogo Ivo
2024-01-17 16:15 ` [PATCH v2 6/8] net: ti: icssg-ethtool: Adjust channel count for SR1.0 Diogo Ivo
2024-01-22 13:42 ` Roger Quadros
2024-01-17 16:15 ` [PATCH v2 7/8] net: ti: iccsg-prueth: Add necessary functions for SR1.0 support Diogo Ivo
2024-01-17 20:56 ` Andrew Lunn
2024-01-17 16:15 ` [PATCH v2 8/8] net: ti: icssg-prueth: Wire up support for SR1.0 Diogo Ivo
2024-01-18 1:16 ` [PATCH v2 0/8] Add support for ICSSG-based Ethernet on SR1.0 devices Jakub Kicinski
2024-01-23 12:15 ` Roger Quadros
2024-01-24 9:24 ` Diogo Ivo
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