From: Srujana Challa <schalla@marvell.com>
To: Herbert Xu <herbert@gondor.apana.org.au>
Cc: "davem@davemloft.net" <davem@davemloft.net>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-crypto@vger.kernel.org" <linux-crypto@vger.kernel.org>,
Suheil Chandran <schandran@marvell.com>,
Narayana Prasad Raju Athreya <pathreya@marvell.com>,
Sunil Kovvuri Goutham <sgoutham@marvell.com>,
Linu Cherian <lcherian@marvell.com>,
"Geethasowjanya Akula" <gakula@marvell.com>,
Jerin Jacob Kollanukkaran <jerinj@marvell.com>
Subject: RE: [PATCH v2 2/3] drivers: crypto: add support for OCTEONTX2 CPT engine
Date: Fri, 4 Sep 2020 13:45:38 +0000 [thread overview]
Message-ID: <BYAPR18MB2791C6451CDE93CA053E0208A02D0@BYAPR18MB2791.namprd18.prod.outlook.com> (raw)
In-Reply-To: <20200813005407.GB24593@gondor.apana.org.au>
> Subject: Re: [PATCH v2 2/3] drivers: crypto: add support for OCTEONTX2 CPT
> engine
>
> On Fri, Aug 07, 2020 at 07:39:19PM +0530, Srujana Challa wrote:
> >
> > +#if defined(CONFIG_ARM64)
> > +static inline long otx2_lmt_flush(void *ioreg)
> > +{
> > + long result = 0;
> > +
> > + __asm__ volatile(".cpu generic+lse\n"
> > + "ldeor xzr, %0, [%1]\n"
> > + : "=r" (result)
> > + : "r" (ioreg) : "memory");
> > +
> > + return result;
> > +}
> > +
> > +#else
> > +#define otx2_lmt_flush(addr) ({ 0; })
> > +#endif
>
> This is not acceptable. Please work out a way with the ARM folks
> to fix this without adding assembly code in a driver.
>
This block of code is used for LMT store operations. The LMT store operation
is specific to our platform, and this uses the "ldeor" instruction(which is
actually an LSE atomic instruction available on v8.1 CPUs) targeting the
IO address.
We add it in the driver since we want LMT store to work even if LSE_ATOMICS
is disabled.
Thanks,
Srujana
> Thanks,
> --
> Email: Herbert Xu <herbert@gondor.apana.org.au>
> Home Page: https://urldefense.proofpoint.com/v2/url?u=http-
> 3A__gondor.apana.org.au_-
> 7Eherbert_&d=DwIBAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=Fj4OoD5hcKFpANhTW
> dwQzjT1Jpf7veC5263T47JVpnc&m=Xm4oQ3dI4peur80298SnMa5gz-
> 1rdAxVE1rwHkmHvc0&s=7S5Z2Mpq-
> th_W_KeJSQIOSo274CMg5UI0Tc9mkUkypg&e=
> PGP Key: https://urldefense.proofpoint.com/v2/url?u=http-
> 3A__gondor.apana.org.au_-
> 7Eherbert_pubkey.txt&d=DwIBAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=Fj4OoD5hcK
> FpANhTWdwQzjT1Jpf7veC5263T47JVpnc&m=Xm4oQ3dI4peur80298SnMa5gz-
> 1rdAxVE1rwHkmHvc0&s=yf6R1d7GDuz4Wmq_7Z7GoPuIkewZfs0x8h6xXvf3b2o&e
> =
next prev parent reply other threads:[~2020-09-04 14:10 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-07 14:09 [PATCH v2 0/3] Add Support for Marvell OcteonTX2 Cryptographic Srujana Challa
2020-08-07 14:09 ` [PATCH v2 1/3] octeontx2-af: add support to manage the CPT unit Srujana Challa
2020-08-07 14:09 ` [PATCH v2 2/3] drivers: crypto: add support for OCTEONTX2 CPT engine Srujana Challa
2020-08-07 15:24 ` Jakub Kicinski
2020-08-13 0:51 ` Herbert Xu
2020-08-13 0:54 ` Herbert Xu
2020-09-04 13:45 ` Srujana Challa [this message]
2020-09-04 13:50 ` Herbert Xu
2020-09-04 14:14 ` [EXT] " Srujana Challa
2020-09-04 14:17 ` Herbert Xu
2020-09-04 16:36 ` Sunil Kovvuri Goutham
2020-09-04 18:38 ` Andrew Lunn
2020-09-08 14:20 ` Srujana Challa
2020-08-07 14:09 ` [PATCH v2 3/3] drivers: crypto: add the Virtual Function driver for OcteonTX2 CPT Srujana Challa
2020-08-13 0:58 ` Herbert Xu
2020-08-08 0:17 ` [PATCH v2 0/3] Add Support for Marvell OcteonTX2 Cryptographic David Miller
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