From: "Wu, Hao" <hao.wu@intel.com>
To: "Xu, Yilun" <yilun.xu@intel.com>,
"Brandeburg, Jesse" <jesse.brandeburg@intel.com>,
"Nguyen, Anthony L" <anthony.l.nguyen@intel.com>,
"davem@davemloft.net" <davem@davemloft.net>,
"kuba@kernel.org" <kuba@kernel.org>,
"mdf@kernel.org" <mdf@kernel.org>,
"lee.jones@linaro.org" <lee.jones@linaro.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-fpga@vger.kernel.org" <linux-fpga@vger.kernel.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"trix@redhat.com" <trix@redhat.com>,
"lgoncalv@redhat.com" <lgoncalv@redhat.com>
Subject: RE: [RFC PATCH 2/6] fpga: dfl: export network configuration info for DFL based FPGA
Date: Mon, 26 Oct 2020 03:29:06 +0000 [thread overview]
Message-ID: <DM6PR11MB381919A632F4A9948B82F92885190@DM6PR11MB3819.namprd11.prod.outlook.com> (raw)
In-Reply-To: <1603442745-13085-3-git-send-email-yilun.xu@intel.com>
> Subject: [RFC PATCH 2/6] fpga: dfl: export network configuration info for DFL
> based FPGA
>
> This patch makes preparation for supporting DFL Ether Group private
> feature driver, which reads bitstream_id.vendor_net_cfg field to
> determin the interconnection of network components on FPGA device.
>
> Signed-off-by: Xu Yilun <yilun.xu@intel.com>
> ---
> drivers/fpga/dfl-fme-main.c | 10 ++--------
> drivers/fpga/dfl.c | 21 +++++++++++++++++++++
> drivers/fpga/dfl.h | 12 ++++++++++++
> include/linux/dfl.h | 2 ++
> 4 files changed, 37 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c
> index 77ea04d..a2b8ba0 100644
> --- a/drivers/fpga/dfl-fme-main.c
> +++ b/drivers/fpga/dfl-fme-main.c
> @@ -46,14 +46,8 @@ static DEVICE_ATTR_RO(ports_num);
> static ssize_t bitstream_id_show(struct device *dev,
> struct device_attribute *attr, char *buf)
> {
> - void __iomem *base;
> - u64 v;
> -
> - base = dfl_get_feature_ioaddr_by_id(dev,
> FME_FEATURE_ID_HEADER);
> -
> - v = readq(base + FME_HDR_BITSTREAM_ID);
> -
> - return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v);
> + return scnprintf(buf, PAGE_SIZE, "0x%llx\n",
> + (unsigned long long)dfl_get_bitstream_id(dev));
> }
> static DEVICE_ATTR_RO(bitstream_id);
>
> diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
> index bc35750..ca3c678 100644
> --- a/drivers/fpga/dfl.c
> +++ b/drivers/fpga/dfl.c
> @@ -537,6 +537,27 @@ void dfl_driver_unregister(struct dfl_driver *dfl_drv)
> }
> EXPORT_SYMBOL(dfl_driver_unregister);
>
> +int dfl_dev_get_vendor_net_cfg(struct dfl_device *dfl_dev)
> +{
> + struct device *fme_dev;
> + u64 v;
> +
> + if (!dfl_dev)
> + return -EINVAL;
> +
> + if (dfl_dev->type == FME_ID)
> + fme_dev = dfl_dev->dev.parent;
> + else
> + fme_dev = dfl_dev->cdev->fme_dev;
All of them have cdev, is my understanding correct?
If so, why handle it differently here?
> +
> + if (!fme_dev)
> + return -EINVAL;
ENODEV?
> +
> + v = dfl_get_bitstream_id(fme_dev);
> + return (int)FIELD_GET(FME_BID_VENDOR_NET_CFG, v);
> +}
> +EXPORT_SYMBOL_GPL(dfl_dev_get_vendor_net_cfg);
> +
> #define is_header_feature(feature) ((feature)->id ==
> FEATURE_ID_FIU_HEADER)
>
> /**
> diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h
> index 2b82c96..6c7a6961 100644
> --- a/drivers/fpga/dfl.h
> +++ b/drivers/fpga/dfl.h
> @@ -104,6 +104,9 @@
> #define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size
> in KB */
> #define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /*
> Associativity */
>
> +/* FME BITSTREAM_ID Register Bitfield */
Bitstream ID, same style as others.
> +#define FME_BID_VENDOR_NET_CFG GENMASK_ULL(35, 32) /* vendor
> net cfg */
> +
> /* FME Port Offset Register Bitfield */
> /* Offset to port device feature header */
> #define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)
> @@ -397,6 +400,15 @@ static inline bool is_dfl_feature_present(struct
> device *dev, u16 id)
> return !!dfl_get_feature_ioaddr_by_id(dev, id);
> }
>
> +static inline u64 dfl_get_bitstream_id(struct device *dev)
> +{
> + void __iomem *base;
> +
> + base = dfl_get_feature_ioaddr_by_id(dev,
> FME_FEATURE_ID_HEADER);
> +
> + return readq(base + FME_HDR_BITSTREAM_ID);
> +}
> +
> static inline
> struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data
> *pdata)
> {
> diff --git a/include/linux/dfl.h b/include/linux/dfl.h
> index e1b2471..5ee2b1e 100644
> --- a/include/linux/dfl.h
> +++ b/include/linux/dfl.h
> @@ -67,6 +67,8 @@ struct dfl_driver {
> #define to_dfl_dev(d) container_of(d, struct dfl_device, dev)
> #define to_dfl_drv(d) container_of(d, struct dfl_driver, drv)
>
> +int dfl_dev_get_vendor_net_cfg(struct dfl_device *dfl_dev);
It seems the vendor net configuration can be provided by a
vendor specific method. So bid_vendor_net_cfg maybe a better name?
Thanks
Hao
> +
> /*
> * use a macro to avoid include chaining to get THIS_MODULE.
> */
> --
> 2.7.4
next prev parent reply other threads:[~2020-10-26 3:29 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 8:45 [RFC PATCH 0/6] Add the netdev support for Intel PAC N3000 FPGA Xu Yilun
2020-10-23 8:45 ` [RFC PATCH 1/6] docs: networking: add the document for DFL Ether Group driver Xu Yilun
2020-10-23 15:37 ` Andrew Lunn
2020-10-26 8:52 ` Xu Yilun
2020-10-26 13:00 ` Andrew Lunn
2020-10-26 17:38 ` Xu Yilun
2020-10-26 18:35 ` Jakub Kicinski
2020-10-27 2:33 ` Xu Yilun
2020-10-26 19:14 ` Andrew Lunn
2020-10-27 3:27 ` Xu Yilun
2020-11-02 2:38 ` Xu Yilun
2020-11-02 14:46 ` Andrew Lunn
2020-10-24 14:25 ` Tom Rix
2020-10-23 8:45 ` [RFC PATCH 2/6] fpga: dfl: export network configuration info for DFL based FPGA Xu Yilun
2020-10-24 13:59 ` Tom Rix
2020-10-26 3:29 ` Wu, Hao [this message]
2020-10-23 8:45 ` [RFC PATCH 3/6] fpga: dfl: add an API to get the base device for dfl device Xu Yilun
2020-10-24 14:39 ` Tom Rix
2020-10-26 3:42 ` Wu, Hao
2020-10-23 8:45 ` [RFC PATCH 4/6] ethernet: m10-retimer: add support for retimers on Intel MAX 10 BMC Xu Yilun
2020-10-24 15:03 ` Tom Rix
2020-10-24 16:39 ` Andrew Lunn
2020-10-24 17:36 ` Tom Rix
2020-10-24 20:33 ` Andrew Lunn
2020-10-23 8:45 ` [RFC PATCH 5/6] ethernet: dfl-eth-group: add DFL eth group private feature driver Xu Yilun
2020-10-24 14:37 ` Andrew Lunn
2020-10-24 17:25 ` Tom Rix
2020-10-25 14:47 ` Andrew Lunn
2020-10-23 8:45 ` [RFC PATCH 6/6] ethernet: dfl-eth-group: add support for the 10G configurations Xu Yilun
2020-10-24 17:43 ` Tom Rix
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