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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2024 23:41:10.7478 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 817ee9f2-6284-446c-a302-08dc5e6eb235 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7553 X-BeenThere: nouveau@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Nouveau development list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: nouveau-bounces@lists.freedesktop.org Sender: "Nouveau" - will help later in the series where display channels apis are modified Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 4 +- drivers/gpu/drm/nouveau/dispnv50/core.c | 39 ++++++++++++++++- drivers/gpu/drm/nouveau/dispnv50/core.h | 4 ++ drivers/gpu/drm/nouveau/dispnv50/core507d.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/corec57d.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/curs507a.c | 6 +-- drivers/gpu/drm/nouveau/dispnv50/disp.c | 27 ------------ drivers/gpu/drm/nouveau/dispnv50/disp.h | 3 -- drivers/gpu/drm/nouveau/dispnv50/head.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 4 +- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 46 +++++++++++++++++++-- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 6 ++- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 4 +- 15 files changed, 104 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index a431f6c5f6fa..0b6fb663d78e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -311,7 +311,7 @@ base507c_new_(const struct nv50_wndw_func *func, const u32 *format, struct nv50_wndw *wndw; int ret; - ret = nv50_wndw_new_(func, drm->dev, DRM_PLANE_TYPE_PRIMARY, + ret = nv50_wndw_prep(func, drm->dev, DRM_PLANE_TYPE_PRIMARY, "base", head, format, BIT(head), NV50_DISP_INTERLOCK_BASE, interlock_data, &wndw); if (*pwndw = wndw, ret) @@ -328,7 +328,7 @@ base507c_new_(const struct nv50_wndw_func *func, const u32 *format, wndw->ntfy = NV50_DISP_BASE_NTFY(wndw->id); wndw->sema = NV50_DISP_BASE_SEM0(wndw->id); wndw->data = 0x00000000; - return 0; + return nv50_wndw_ctor(wndw); } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/core.c b/drivers/gpu/drm/nouveau/dispnv50/core.c index f045515696cb..1864f3e3bbc3 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core.c +++ b/drivers/gpu/drm/nouveau/dispnv50/core.c @@ -20,14 +20,20 @@ * OTHER DEALINGS IN THE SOFTWARE. */ #include "core.h" +#include "handles.h" + +#include "nouveau_bo.h" #include +#include void nv50_core_del(struct nv50_core **pcore) { struct nv50_core *core = *pcore; if (core) { + nvif_object_dtor(&core->sync); + nvif_object_dtor(&core->vram); nv50_dmac_destroy(&core->chan); kfree(*pcore); *pcore = NULL; @@ -61,7 +67,9 @@ nv50_core_new(struct nouveau_drm *drm, struct nv50_core **pcore) {} }; struct nv50_disp *disp = nv50_disp(drm->dev); + struct nv50_core *core; int cid; + int ret; cid = nvif_mclass(&disp->disp->object, cores); if (cid < 0) { @@ -69,5 +77,34 @@ nv50_core_new(struct nouveau_drm *drm, struct nv50_core **pcore) return cid; } - return cores[cid].new(drm, cores[cid].oclass, pcore); + ret = cores[cid].new(drm, cores[cid].oclass, &core); + *pcore = core; + if (ret) + return ret; + + ret = nvif_object_ctor(&core->chan.base.user, "kmsCoreSyncCtxdma", NV50_DISP_HANDLE_SYNCBUF, + NV_DMA_IN_MEMORY, + &(struct nv_dma_v0) { + .target = NV_DMA_V0_TARGET_VRAM, + .access = NV_DMA_V0_ACCESS_RDWR, + .start = disp->sync->offset + 0x0000, + .limit = disp->sync->offset + 0x0fff, + }, sizeof(struct nv_dma_v0), + &core->sync); + if (ret) + return ret; + + ret = nvif_object_ctor(&core->chan.base.user, "kmsCoreVramCtxdma", NV50_DISP_HANDLE_VRAM, + NV_DMA_IN_MEMORY, + &(struct nv_dma_v0) { + .target = NV_DMA_V0_TARGET_VRAM, + .access = NV_DMA_V0_ACCESS_RDWR, + .start = 0, + .limit = drm->device.info.ram_user - 1, + }, sizeof(struct nv_dma_v0), + &core->vram); + if (ret) + return ret; + + return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/core.h b/drivers/gpu/drm/nouveau/dispnv50/core.h index f75088186fba..a967c66dc7a2 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core.h +++ b/drivers/gpu/drm/nouveau/dispnv50/core.h @@ -8,6 +8,10 @@ struct nv50_core { const struct nv50_core_func *func; struct nv50_dmac chan; + + struct nvif_object vram; + struct nvif_object sync; + bool assign_windows; }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/core507d.c b/drivers/gpu/drm/nouveau/dispnv50/core507d.c index ce2cb78bbdd3..c6eee88ae99a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/core507d.c @@ -136,7 +136,7 @@ core507d_init(struct nv50_core *core) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_MTHD(push, NV507D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle); + PUSH_MTHD(push, NV507D, SET_CONTEXT_DMA_NOTIFIER, core->sync.handle); return PUSH_KICK(push); } diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c index 7f637b8830be..9525fd30c8fc 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c @@ -134,7 +134,7 @@ corec37d_init(struct nv50_core *core) if ((ret = PUSH_WAIT(push, 2 + windows * 5))) return ret; - PUSH_MTHD(push, NVC37D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle); + PUSH_MTHD(push, NVC37D, SET_CONTEXT_DMA_NOTIFIER, core->sync.handle); for (i = 0; i < windows; i++) { PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i), diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec57d.c b/drivers/gpu/drm/nouveau/dispnv50/corec57d.c index 421d0d57e1d8..485892c2e775 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec57d.c @@ -36,7 +36,7 @@ corec57d_init(struct nv50_core *core) if ((ret = PUSH_WAIT(push, 2 + windows * 5))) return ret; - PUSH_MTHD(push, NVC57D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle); + PUSH_MTHD(push, NVC57D, SET_CONTEXT_DMA_NOTIFIER, core->sync.handle); for (i = 0; i < windows; i++) { PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i), diff --git a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c index a95ee5dcc2e3..7292d1554dba 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c +++ b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c @@ -78,7 +78,7 @@ static void curs507a_prepare(struct nv50_wndw *wndw, struct nv50_head_atom *asyh, struct nv50_wndw_atom *asyw) { - u32 handle = nv50_disp(wndw->plane.dev)->core->chan.vram.handle; + u32 handle = nv50_disp(wndw->plane.dev)->core->vram.handle; u32 offset = asyw->image.offset[0]; if (asyh->curs.handle != handle || asyh->curs.offset != offset) { asyh->curs.handle = handle; @@ -177,7 +177,7 @@ curs507a_new_(const struct nv50_wimm_func *func, struct nouveau_drm *drm, struct nv50_wndw *wndw; int ret; - ret = nv50_wndw_new_(&curs507a_wndw, drm->dev, DRM_PLANE_TYPE_CURSOR, + ret = nv50_wndw_prep(&curs507a_wndw, drm->dev, DRM_PLANE_TYPE_CURSOR, "curs", head, curs507a_format, BIT(head), NV50_DISP_INTERLOCK_CURS, interlock_data, &wndw); if (*pwndw = wndw, ret) @@ -193,7 +193,7 @@ curs507a_new_(const struct nv50_wimm_func *func, struct nouveau_drm *drm, nvif_object_map(&wndw->wimm.base.user, NULL, 0); wndw->immd = func; wndw->ctxdma.parent = NULL; - return 0; + return nv50_wndw_ctor(wndw); } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 125c33ee251a..31b46a62b501 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -119,9 +119,6 @@ nv50_chan_destroy(struct nv50_chan *chan) void nv50_dmac_destroy(struct nv50_dmac *dmac) { - nvif_object_dtor(&dmac->vram); - nvif_object_dtor(&dmac->sync); - nv50_chan_destroy(&dmac->base); nvif_mem_dtor(&dmac->push.mem); @@ -280,30 +277,6 @@ nv50_dmac_create(struct nouveau_drm *drm, if (syncbuf < 0) return 0; - ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF, - NV_DMA_IN_MEMORY, - &(struct nv_dma_v0) { - .target = NV_DMA_V0_TARGET_VRAM, - .access = NV_DMA_V0_ACCESS_RDWR, - .start = syncbuf + 0x0000, - .limit = syncbuf + 0x0fff, - }, sizeof(struct nv_dma_v0), - &dmac->sync); - if (ret) - return ret; - - ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM, - NV_DMA_IN_MEMORY, - &(struct nv_dma_v0) { - .target = NV_DMA_V0_TARGET_VRAM, - .access = NV_DMA_V0_ACCESS_RDWR, - .start = 0, - .limit = device->info.ram_user - 1, - }, sizeof(struct nv_dma_v0), - &dmac->vram); - if (ret) - return ret; - return ret; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.h b/drivers/gpu/drm/nouveau/dispnv50/disp.h index a7a01ae77ff4..9485f8c90cac 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.h +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.h @@ -63,9 +63,6 @@ struct nv50_dmac { struct nv50_chan base; struct nvif_push push; - - struct nvif_object sync; - struct nvif_object vram; }; struct nv50_outp_atom { diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c b/drivers/gpu/drm/nouveau/dispnv50/head.c index 83355dbc15ee..007857ac8542 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c @@ -274,7 +274,7 @@ nv50_head_atomic_check_lut(struct nv50_head *head, size, crtc->base.id, crtc->name); return -EINVAL; } - asyh->olut.handle = disp->core->chan.vram.handle; + asyh->olut.handle = disp->core->vram.handle; asyh->olut.buffer = !asyh->olut.buffer; return 0; diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index 7fa1e0279d7d..634f6166f38d 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -265,7 +265,7 @@ head507d_core_calc(struct nv50_head *head, struct nv50_head_atom *asyh) asyh->core.w = asyh->state.mode.hdisplay; asyh->core.h = asyh->state.mode.vdisplay; } - asyh->core.handle = disp->core->chan.vram.handle; + asyh->core.handle = disp->core->vram.handle; asyh->core.offset = 0; asyh->core.format = NV507D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8; asyh->core.kind = NV507D_HEAD_SET_PARAMS_KIND_KIND_PITCH; diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c index 654e506f8431..4e109c5b5a1b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c @@ -152,7 +152,7 @@ ovly507e_new_(const struct nv50_wndw_func *func, const u32 *format, struct nv50_wndw *wndw; int ret; - ret = nv50_wndw_new_(func, drm->dev, DRM_PLANE_TYPE_OVERLAY, + ret = nv50_wndw_prep(func, drm->dev, DRM_PLANE_TYPE_OVERLAY, "ovly", head, format, BIT(head), NV50_DISP_INTERLOCK_OVLY, interlock_data, &wndw); @@ -170,7 +170,7 @@ ovly507e_new_(const struct nv50_wndw_func *func, const u32 *format, wndw->ntfy = NV50_DISP_OVLY_NTFY(wndw->id); wndw->sema = NV50_DISP_OVLY_SEM0(wndw->id); wndw->data = 0x00000000; - return 0; + return nv50_wndw_ctor(wndw); } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 7a2cceaee6e9..1dbf0e73b5de 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -181,7 +181,7 @@ nv50_wndw_ntfy_enable(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { struct nv50_disp *disp = nv50_disp(wndw->plane.dev); - asyw->ntfy.handle = wndw->wndw.sync.handle; + asyw->ntfy.handle = wndw->sync.handle; asyw->ntfy.offset = wndw->ntfy; asyw->ntfy.awaken = false; asyw->set.ntfy = true; @@ -406,7 +406,7 @@ nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw, memset(&asyw->xlut, 0x00, sizeof(asyw->xlut)); if ((asyw->ilut = wndw->func->ilut ? ilut : NULL)) { wndw->func->ilut(wndw, asyw, drm_color_lut_size(ilut)); - asyw->xlut.handle = wndw->wndw.vram.handle; + asyw->xlut.handle = wndw->vram.handle; asyw->xlut.i.buffer = !asyw->xlut.i.buffer; asyw->set.xlut = true; } else { @@ -645,6 +645,9 @@ nv50_wndw_destroy(struct drm_plane *plane) } nv50_dmac_destroy(&wndw->wimm); + + nvif_object_dtor(&wndw->vram); + nvif_object_dtor(&wndw->sync); nv50_dmac_destroy(&wndw->wndw); nv50_lut_fini(&wndw->ilut); @@ -693,7 +696,44 @@ static const u64 nv50_cursor_format_modifiers[] = { }; int -nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, +nv50_wndw_ctor(struct nv50_wndw *wndw) +{ + struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); + struct nv50_disp *disp = nv50_disp(wndw->plane.dev); + int ret; + + if (!nvif_object_constructed(&wndw->wndw.base.user)) + return 0; + + ret = nvif_object_ctor(&wndw->wndw.base.user, "kmsWndwSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF, + NV_DMA_IN_MEMORY, + &(struct nv_dma_v0) { + .target = NV_DMA_V0_TARGET_VRAM, + .access = NV_DMA_V0_ACCESS_RDWR, + .start = disp->sync->offset + 0x0000, + .limit = disp->sync->offset + 0x0fff, + }, sizeof(struct nv_dma_v0), + &wndw->sync); + if (ret) + return ret; + + ret = nvif_object_ctor(&wndw->wndw.base.user, "kmsWndwVramCtxDma", NV50_DISP_HANDLE_VRAM, + NV_DMA_IN_MEMORY, + &(struct nv_dma_v0) { + .target = NV_DMA_V0_TARGET_VRAM, + .access = NV_DMA_V0_ACCESS_RDWR, + .start = 0, + .limit = drm->device.info.ram_user - 1, + }, sizeof(struct nv_dma_v0), + &wndw->vram); + if (ret) + return ret; + + return 0; +} + +int +nv50_wndw_prep(const struct nv50_wndw_func *func, struct drm_device *dev, enum drm_plane_type type, const char *name, int index, const u32 *format, u32 heads, enum nv50_disp_interlock_type interlock_type, u32 interlock_data, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 76a6ae5d5652..66a06e20a6a0 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -28,16 +28,20 @@ struct nv50_wndw { struct nv50_dmac wndw; struct nv50_dmac wimm; + struct nvif_object vram; + struct nvif_object sync; + u16 ntfy; u16 sema; u32 data; }; -int nv50_wndw_new_(const struct nv50_wndw_func *, struct drm_device *, +int nv50_wndw_prep(const struct nv50_wndw_func *, struct drm_device *, enum drm_plane_type, const char *name, int index, const u32 *format, u32 heads, enum nv50_disp_interlock_type, u32 interlock_data, struct nv50_wndw **); +int nv50_wndw_ctor(struct nv50_wndw *); void nv50_wndw_flush_set(struct nv50_wndw *, u32 *interlock, struct nv50_wndw_atom *); void nv50_wndw_flush_clr(struct nv50_wndw *, u32 *interlock, bool flush, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 50a7b97d37a2..5029dfd98443 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -357,7 +357,7 @@ wndwc37e_new_(const struct nv50_wndw_func *func, struct nouveau_drm *drm, struct nv50_wndw *wndw; int ret; - ret = nv50_wndw_new_(func, drm->dev, type, "wndw", index, + ret = nv50_wndw_prep(func, drm->dev, type, "wndw", index, wndwc37e_format, heads, NV50_DISP_INTERLOCK_WNDW, BIT(index), &wndw); if (*pwndw = wndw, ret) @@ -374,7 +374,7 @@ wndwc37e_new_(const struct nv50_wndw_func *func, struct nouveau_drm *drm, wndw->ntfy = NV50_DISP_WNDW_NTFY(wndw->id); wndw->sema = NV50_DISP_WNDW_SEM0(wndw->id); wndw->data = 0x00000000; - return 0; + return nv50_wndw_ctor(wndw); } int -- 2.41.0