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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: "Ho-Ren (Jack) Chuang" <horenchuang@bytedance.com>
Cc: "Huang, Ying" <ying.huang@intel.com>,
	Gregory Price <gourry.memverge@gmail.com>,
	<aneesh.kumar@linux.ibm.com>, <mhocko@suse.com>, <tj@kernel.org>,
	<john@jagalactic.com>, Eishan Mirakhur <emirakhur@micron.com>,
	Vinicius Tavares Petrucci <vtavarespetr@micron.com>,
	Ravis OpenSrc <Ravis.OpenSrc@micron.com>,
	Alistair Popple <apopple@nvidia.com>,
	Srinivasulu Thanneeru <sthanneeru@micron.com>,
	SeongJae Park <sj@kernel.org>,
	Dan Williams <dan.j.williams@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	"Dave Jiang" <dave.jiang@intel.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	<nvdimm@lists.linux.dev>, <linux-cxl@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-mm@kvack.org>,
	"Ho-Ren (Jack) Chuang" <horenc@vt.edu>,
	"Ho-Ren (Jack) Chuang" <horenchuang@gmail.com>,
	<qemu-devel@nongnu.org>, Hao Xiang <hao.xiang@bytedance.com>
Subject: Re: [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info
Date: Fri, 19 Apr 2024 15:01:34 +0100	[thread overview]
Message-ID: <20240419150134.000032ff@Huawei.com> (raw)
In-Reply-To: <20240405000707.2670063-3-horenchuang@bytedance.com>

On Fri,  5 Apr 2024 00:07:06 +0000
"Ho-Ren (Jack) Chuang" <horenchuang@bytedance.com> wrote:

> The current implementation treats emulated memory devices, such as
> CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory
> (E820_TYPE_RAM). However, these emulated devices have different
> characteristics than traditional DRAM, making it important to
> distinguish them. Thus, we modify the tiered memory initialization process
> to introduce a delay specifically for CPUless NUMA nodes. This delay
> ensures that the memory tier initialization for these nodes is deferred
> until HMAT information is obtained during the boot process. Finally,
> demotion tables are recalculated at the end.
> 
> * late_initcall(memory_tier_late_init);
> Some device drivers may have initialized memory tiers between
> `memory_tier_init()` and `memory_tier_late_init()`, potentially bringing
> online memory nodes and configuring memory tiers. They should be excluded
> in the late init.
> 
> * Handle cases where there is no HMAT when creating memory tiers
> There is a scenario where a CPUless node does not provide HMAT information.
> If no HMAT is specified, it falls back to using the default DRAM tier.
> 
> * Introduce another new lock `default_dram_perf_lock` for adist calculation
> In the current implementation, iterating through CPUlist nodes requires
> holding the `memory_tier_lock`. However, `mt_calc_adistance()` will end up
> trying to acquire the same lock, leading to a potential deadlock.
> Therefore, we propose introducing a standalone `default_dram_perf_lock` to
> protect `default_dram_perf_*`. This approach not only avoids deadlock
> but also prevents holding a large lock simultaneously.
> 
> * Upgrade `set_node_memory_tier` to support additional cases, including
>   default DRAM, late CPUless, and hot-plugged initializations.
> To cover hot-plugged memory nodes, `mt_calc_adistance()` and
> `mt_find_alloc_memory_type()` are moved into `set_node_memory_tier()` to
> handle cases where memtype is not initialized and where HMAT information is
> available.
> 
> * Introduce `default_memory_types` for those memory types that are not
>   initialized by device drivers.
> Because late initialized memory and default DRAM memory need to be managed,
> a default memory type is created for storing all memory types that are
> not initialized by device drivers and as a fallback.
> 
> Signed-off-by: Ho-Ren (Jack) Chuang <horenchuang@bytedance.com>
> Signed-off-by: Hao Xiang <hao.xiang@bytedance.com>
> Reviewed-by: "Huang, Ying" <ying.huang@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

      parent reply	other threads:[~2024-04-19 14:01 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-05  0:07 [PATCH v11 0/2] Improved Memory Tier Creation for CPUless NUMA Nodes Ho-Ren (Jack) Chuang
2024-04-05  0:07 ` [PATCH v11 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types Ho-Ren (Jack) Chuang
2024-04-05 13:56   ` Jonathan Cameron
2024-04-09 19:00     ` [External] " Ho-Ren (Jack) Chuang
2024-04-09 21:50       ` Andrew Morton
2024-04-09 23:09         ` Ho-Ren (Jack) Chuang
2024-04-05  0:07 ` [PATCH v11 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info Ho-Ren (Jack) Chuang
2024-04-05 14:02   ` Jonathan Cameron
2024-04-05 22:43     ` Ho-Ren (Jack) Chuang
2024-04-09 16:12       ` Jonathan Cameron
2024-04-09 19:02         ` [External] " Ho-Ren (Jack) Chuang
2024-04-10 16:51           ` Jonathan Cameron
2024-04-17  8:53             ` Ho-Ren (Jack) Chuang
2024-04-10  2:30       ` Huang, Ying
2024-04-10  5:55         ` [External] " Ho-Ren (Jack) Chuang
2024-04-19 14:01   ` Jonathan Cameron [this message]

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