From: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
To: <robh+dt@kernel.org>, <joel@jms.id.au>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <adrian.hunter@intel.com>,
<linux-aspeed@lists.ozlabs.org>, <openbmc@lists.ozlabs.org>,
<linux-mmc@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<andrew@aj.id.au>
Cc: BMC-SW@aspeedtech.com, steven_lee@aspeedtech.com
Subject: [PATCH 02/10] sdhci: aspeed: Add SDR50 support
Date: Wed, 22 Sep 2021 18:31:08 +0800 [thread overview]
Message-ID: <20210922103116.30652-3-chin-ting_kuo@aspeedtech.com> (raw)
In-Reply-To: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com>
From the analog waveform analysis result, SD/SDIO controller
of AST2600 cannot always work well with 200MHz. The upper bound
stable frequency for SD/SDIO controller is 100MHz. Thus, SDR50
supported bit, instead of SDR104, in capability 2 register
should be set in advance.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
---
drivers/mmc/host/sdhci-of-aspeed.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c
index 6e4e132903a6..c6eaeb02e3f9 100644
--- a/drivers/mmc/host/sdhci-of-aspeed.c
+++ b/drivers/mmc/host/sdhci-of-aspeed.c
@@ -35,6 +35,8 @@
#define ASPEED_SDC_CAP1_1_8V (0 * 32 + 26)
/* SDIO{14,24} */
#define ASPEED_SDC_CAP2_SDR104 (1 * 32 + 1)
+/* SDIO{14,24} */
+#define ASPEED_SDC_CAP2_SDR50 (1 * 32 + 0)
struct aspeed_sdc {
struct clk *clk;
@@ -410,11 +412,17 @@ static int aspeed_sdhci_probe(struct platform_device *pdev)
sdhci_get_of_property(pdev);
if (of_property_read_bool(np, "mmc-hs200-1_8v") ||
+ of_property_read_bool(np, "sd-uhs-sdr50") ||
of_property_read_bool(np, "sd-uhs-sdr104")) {
aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP1_1_8V,
true, slot);
}
+ if (of_property_read_bool(np, "sd-uhs-sdr50")) {
+ aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP2_SDR50,
+ true, slot);
+ }
+
if (of_property_read_bool(np, "sd-uhs-sdr104")) {
aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP2_SDR104,
true, slot);
--
2.17.1
next prev parent reply other threads:[~2021-09-22 11:05 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-22 10:31 [PATCH 00/10] ASPEED SD/eMMC controller clock configuration Chin-Ting Kuo
2021-09-22 10:31 ` [PATCH 01/10] clk: aspeed: ast2600: Porting sdhci clock source Chin-Ting Kuo
2021-09-23 0:02 ` Joel Stanley
2021-09-23 5:31 ` Chin-Ting Kuo
2021-10-26 6:10 ` Paul Menzel
2021-11-26 2:27 ` Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo [this message]
2021-10-26 0:31 ` [PATCH 02/10] sdhci: aspeed: Add SDR50 support Andrew Jeffery
2021-11-06 10:01 ` Chin-Ting Kuo
2021-09-22 10:31 ` [PATCH 03/10] dts: aspeed: ast2600: Support SDR50 for SD device Chin-Ting Kuo
2021-10-26 0:42 ` Andrew Jeffery
2021-11-06 10:01 ` Chin-Ting Kuo
2021-09-22 10:31 ` [PATCH 04/10] mmc: Add invert flag for clock phase signedness Chin-Ting Kuo
2021-10-26 0:52 ` Andrew Jeffery
2021-11-06 10:02 ` Chin-Ting Kuo
2021-11-08 0:21 ` Andrew Jeffery
2021-09-22 10:31 ` [PATCH 05/10] mmc: aspeed: Adjust delay taps calculation method Chin-Ting Kuo
2021-10-26 3:10 ` Andrew Jeffery
2021-11-06 10:05 ` Chin-Ting Kuo
2021-11-07 23:42 ` Andrew Jeffery
2021-09-22 10:31 ` [PATCH 06/10] arm: dts: aspeed: Change eMMC device compatible Chin-Ting Kuo
2021-09-22 10:31 ` [PATCH 07/10] arm: dts: aspeed: Adjust clock phase parameter Chin-Ting Kuo
2021-09-22 10:31 ` [PATCH 08/10] arm: dts: ibm: " Chin-Ting Kuo
2021-09-22 10:31 ` [PATCH 09/10] dt-bindings: mmc: aspeed: Add max-tap-delay property Chin-Ting Kuo
2021-09-27 18:40 ` Rob Herring
2021-09-28 2:50 ` Chin-Ting Kuo
2021-09-22 10:31 ` [PATCH 10/10] dt-bindings: mmc: aspeed: Add a new compatible string Chin-Ting Kuo
2021-09-27 18:59 ` Rob Herring
2021-09-28 2:50 ` Chin-Ting Kuo
2021-09-28 22:28 ` Rob Herring
2021-09-29 3:03 ` Chin-Ting Kuo
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