From: Bjorn Helgaas <helgaas@kernel.org>
To: "David E. Box" <david.e.box@linux.intel.com>
Cc: lee.jones@linaro.org, dvhart@infradead.org, andy@infradead.org,
bhelgaas@google.com, hdegoede@redhat.com,
alexey.budankov@linux.intel.com,
Andy Shevchenko <andy.shevchenko@gmail.com>,
rjw@rjwysocki.net, linux-kernel@vger.kernel.org,
platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH V8 1/5] PCI: Add defines for Designated Vendor-Specific Extended Capability
Date: Tue, 6 Oct 2020 19:51:18 -0500 [thread overview]
Message-ID: <20201007005118.GA3230211@bjorn-Precision-5520> (raw)
In-Reply-To: <b75c3ff53dbe26ee0c6825e8d1f5f10489a5722c.camel@linux.intel.com>
On Tue, Oct 06, 2020 at 03:45:54PM -0700, David E. Box wrote:
> Hi Bjorn,
>
> This patch has been acked and unchanged for weeks. Is it possible to
> get this pulled into next? We have SIOV and CXL related work that is
> using these definitions. Thanks.
I acked it because I expected you to merge it along with the rest of
the series.
I guess I could merge this patch via the PCI tree if you really want,
but that ends up being a hassle because we have to worry about which
order things get merged to Linus' tree. Better if the whole series is
merged via the same tree.
> On Fri, 2020-10-02 at 18:31 -0700, David E. Box wrote:
> > Add PCIe Designated Vendor-Specific Extended Capability (DVSEC) and
> > defines
> > for the header offsets. Defined in PCIe r5.0, sec 7.9.6.
> >
> > Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> > Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> > Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> > ---
> > include/uapi/linux/pci_regs.h | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/include/uapi/linux/pci_regs.h
> > b/include/uapi/linux/pci_regs.h
> > index f9701410d3b5..beafeee39e44 100644
> > --- a/include/uapi/linux/pci_regs.h
> > +++ b/include/uapi/linux/pci_regs.h
> > @@ -720,6 +720,7 @@
> > #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port
> > Containment */
> > #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
> > #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement
> > */
> > +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific
> > */
> > #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
> > #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer
> > 16.0 GT/s */
> > #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT
> > @@ -1062,6 +1063,10 @@
> > #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /*
> > LTR_L1.2_THRESHOLD_Scale */
> > #define PCI_L1SS_CTL2 0x0c /* Control 2 Register
> > */
> >
> > +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
> > +#define PCI_DVSEC_HEADER1 0x4 /* Designated Vendor-
> > Specific Header1 */
> > +#define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-
> > Specific Header2 */
> > +
> > /* Data Link Feature */
> > #define PCI_DLF_CAP 0x04 /* Capabilities Register */
> > #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link
> > Feature Exchange Enable */
>
next prev parent reply other threads:[~2020-10-07 0:51 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-03 1:31 [PATCH V8 0/5] Intel Platform Monitoring Technology David E. Box
2020-10-03 1:31 ` [PATCH V8 1/5] PCI: Add defines for Designated Vendor-Specific Extended Capability David E. Box
2020-10-06 22:45 ` David E. Box
2020-10-07 0:51 ` Bjorn Helgaas [this message]
2020-10-07 1:47 ` David E. Box
2020-10-07 6:54 ` Lee Jones
2020-10-07 21:36 ` Hans de Goede
2020-10-08 7:29 ` Lee Jones
2020-10-08 11:13 ` Hans de Goede
2020-10-03 1:31 ` [PATCH V8 2/5] mfd: Intel Platform Monitoring Technology support David E. Box
2020-10-07 6:57 ` Lee Jones
2020-10-07 16:10 ` David E. Box
2020-10-08 7:32 ` Lee Jones
2020-11-10 10:39 ` Geert Uytterhoeven
2020-11-10 18:06 ` David E. Box
2020-10-03 1:31 ` [PATCH V8 3/5] platform/x86: Intel PMT class driver David E. Box
2020-10-03 1:31 ` [PATCH V8 4/5] platform/x86: Intel PMT Telemetry capability driver David E. Box
2020-10-03 1:31 ` [PATCH V8 5/5] platform/x86: Intel PMT Crashlog " David E. Box
2020-10-27 11:28 ` [PATCH V8 0/5] Intel Platform Monitoring Technology Hans de Goede
2020-10-29 1:50 ` David E. Box
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