From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Yong-Xuan Wang <yongxuan.wang@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
rkanwal@rivosinc.com, anup@brainfault.org, atishp@atishpatra.org,
vincent.chen@sifive.com, greentime.hu@sifive.com,
frank.chang@sifive.com, jim.shu@sifive.com
Cc: "Alistair Francis" <alistair.francis@wdc.com>,
"Stefan Weil" <sw@weilnetz.de>,
"Mayuresh Chitale" <mchitale@ventanamicro.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Palmer Dabbelt" <palmer@rivosinc.com>
Subject: Re: [PATCH v3 5/6] target/riscv: update APLIC and IMSIC to support KVM AIA
Date: Tue, 6 Jun 2023 10:47:40 -0300 [thread overview]
Message-ID: <0a27afe3-0749-99cb-772e-0970e7dda20f@ventanamicro.com> (raw)
In-Reply-To: <20230526062509.31682-6-yongxuan.wang@sifive.com>
On 5/26/23 03:25, Yong-Xuan Wang wrote:
> - Do not set the mmio operations of APLIC and IMSIC when using KVM AIA
> - Send interrupt signal to KVM AIA via KVM_IRQ_LINE API
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> hw/intc/riscv_aplic.c | 19 +++++++++++++++----
> hw/intc/riscv_imsic.c | 16 +++++++++++-----
> 2 files changed, 26 insertions(+), 9 deletions(-)
>
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> index afc5b54dbb..adf5427f22 100644
> --- a/hw/intc/riscv_aplic.c
> +++ b/hw/intc/riscv_aplic.c
> @@ -31,6 +31,7 @@
> #include "hw/irq.h"
> #include "target/riscv/cpu.h"
> #include "sysemu/sysemu.h"
> +#include "sysemu/kvm.h"
> #include "migration/vmstate.h"
>
> #define APLIC_MAX_IDC (1UL << 14)
> @@ -479,6 +480,11 @@ static void riscv_aplic_request(void *opaque, int irq, int level)
>
> assert((0 < irq) && (irq < aplic->num_irqs));
>
> + if (kvm_irqchip_in_kernel()) {
> + kvm_set_irq(kvm_state, irq, !!level);
> + return;
> + }
> +
> sourcecfg = aplic->sourcecfg[irq];
> if (sourcecfg & APLIC_SOURCECFG_D) {
> childidx = sourcecfg & APLIC_SOURCECFG_CHILDIDX_MASK;
> @@ -814,9 +820,11 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
> aplic->iforce = g_new0(uint32_t, aplic->num_harts);
> aplic->ithreshold = g_new0(uint32_t, aplic->num_harts);
>
> - memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, aplic,
> - TYPE_RISCV_APLIC, aplic->aperture_size);
> - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
> + if (!kvm_irqchip_in_kernel()) {
> + memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops,
> + aplic, TYPE_RISCV_APLIC, aplic->aperture_size);
> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
> + }
>
> /*
> * Only root APLICs have hardware IRQ lines. All non-root APLICs
> @@ -958,7 +966,10 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
> qdev_prop_set_bit(dev, "mmode", mmode);
>
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
> +
> + if (!kvm_irqchip_in_kernel()) {
> + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
> + }
>
> if (parent) {
> riscv_aplic_add_child(parent, dev);
> diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
> index fea3385b51..8bfa480f7c 100644
> --- a/hw/intc/riscv_imsic.c
> +++ b/hw/intc/riscv_imsic.c
> @@ -32,6 +32,7 @@
> #include "target/riscv/cpu.h"
> #include "target/riscv/cpu_bits.h"
> #include "sysemu/sysemu.h"
> +#include "sysemu/kvm.h"
> #include "migration/vmstate.h"
>
> #define IMSIC_MMIO_PAGE_LE 0x00
> @@ -325,10 +326,12 @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp)
> imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);
> imsic->eistate = g_new0(uint32_t, imsic->num_eistate);
>
> - memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops,
> - imsic, TYPE_RISCV_IMSIC,
> - IMSIC_MMIO_SIZE(imsic->num_pages));
> - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio);
> + if (!kvm_irqchip_in_kernel()) {
> + memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops,
> + imsic, TYPE_RISCV_IMSIC,
> + IMSIC_MMIO_SIZE(imsic->num_pages));
> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio);
> + }
>
> /* Claim the CPU interrupt to be triggered by this IMSIC */
> if (riscv_cpu_claim_interrupts(rcpu,
> @@ -432,7 +435,10 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
> qdev_prop_set_uint32(dev, "num-irqs", num_ids + 1);
>
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
> +
> + if (!kvm_irqchip_in_kernel()) {
> + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
> + }
>
> for (i = 0; i < num_pages; i++) {
> if (!i) {
next prev parent reply other threads:[~2023-06-06 13:48 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-26 6:25 [PATCH v3 0/6] Add RISC-V KVM AIA Support Yong-Xuan Wang
2023-05-26 6:25 ` [PATCH v3 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support placeholder Yong-Xuan Wang
2023-05-26 6:25 ` [PATCH v3 2/6] target/riscv: support the AIA device emulation with KVM enabled Yong-Xuan Wang
2023-06-05 18:45 ` Daniel Henrique Barboza
2023-06-12 6:50 ` Yong-Xuan Wang
2023-06-14 9:13 ` Daniel Henrique Barboza
2023-05-26 6:25 ` [PATCH v3 3/6] target/riscv: check the in-kernel irqchip support Yong-Xuan Wang
2023-06-05 18:47 ` Daniel Henrique Barboza
2023-05-26 6:25 ` [PATCH v3 4/6] target/riscv: Create an KVM AIA irqchip Yong-Xuan Wang
2023-06-06 13:45 ` Daniel Henrique Barboza
2023-06-09 10:09 ` Yong-Xuan Wang
2023-05-26 6:25 ` [PATCH v3 5/6] target/riscv: update APLIC and IMSIC to support KVM AIA Yong-Xuan Wang
2023-06-06 13:47 ` Daniel Henrique Barboza [this message]
2023-05-26 6:25 ` [PATCH v3 6/6] target/riscv: select KVM AIA in riscv virt machine Yong-Xuan Wang
2023-06-06 13:48 ` Daniel Henrique Barboza
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