From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 2/7] target-arm: Implement MDCR_EL3 and SDCR
Date: Sat, 6 Feb 2016 13:04:03 +0100 [thread overview]
Message-ID: <20160206120403.GB3913@toto> (raw)
In-Reply-To: <1454506721-11843-3-git-send-email-peter.maydell@linaro.org>
On Wed, Feb 03, 2016 at 01:38:36PM +0000, Peter Maydell wrote:
> Implement the MDCR_EL3 register (which is SDCR for AArch32).
> For the moment we implement it as reads-as-written.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/cpu.h | 1 +
> target-arm/helper.c | 24 ++++++++++++++++++++++++
> 2 files changed, 25 insertions(+)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 52284e9..cf2df50 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -382,6 +382,7 @@ typedef struct CPUARMState {
> uint64_t mdscr_el1;
> uint64_t oslsr_el1; /* OS Lock Status */
> uint64_t mdcr_el2;
> + uint64_t mdcr_el3;
Should we maybe arrayify these even if we waste space?
Anyway:
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> /* If the counter is enabled, this stores the last time the counter
> * was reset. Otherwise it stores the counter value
> */
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index b631b83..8b96b80 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -364,6 +364,23 @@ static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
> return CP_ACCESS_OK;
> }
>
> +/* Some secure-only AArch32 registers trap to EL3 if used from
> + * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
> + * We assume that the .access field is set to PL1_RW.
> + */
> +static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
> + const ARMCPRegInfo *ri)
> +{
> + if (arm_current_el(env) == 3) {
> + return CP_ACCESS_OK;
> + }
> + if (arm_is_secure_below_el3(env)) {
> + return CP_ACCESS_TRAP_EL3;
> + }
> + /* This will be EL1 NS and EL2 NS, which just UNDEF */
> + return CP_ACCESS_TRAP_UNCATEGORIZED;
> +}
> +
> static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
> {
> ARMCPU *cpu = arm_env_get_cpu(env);
> @@ -3532,6 +3549,13 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
> .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
> .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
> .writefn = scr_write },
> + { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
> + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
> + { .name = "SDCR", .type = ARM_CP_ALIAS,
> + .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
> + .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
> + .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
> { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
> .access = PL3_RW, .resetvalue = 0,
> --
> 1.9.1
>
next prev parent reply other threads:[~2016-02-06 12:10 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-03 13:38 [Qemu-devel] [PATCH 0/7] Fix some more EL3 things and enable EL3 for AArch64 Peter Maydell
2016-02-03 13:38 ` [Qemu-devel] [PATCH 1/7] target-arm: Fix typo in comment in arm_is_secure_below_el3() Peter Maydell
2016-02-05 9:52 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2016-02-06 11:49 ` [Qemu-devel] " Edgar E. Iglesias
2016-02-06 18:24 ` [Qemu-devel] [Qemu-arm] " Sergey Fedorov
2016-02-03 13:38 ` [Qemu-devel] [PATCH 2/7] target-arm: Implement MDCR_EL3 and SDCR Peter Maydell
2016-02-05 11:13 ` Alex Bennée
2016-02-05 11:28 ` Peter Maydell
2016-02-06 12:04 ` Edgar E. Iglesias [this message]
2016-02-06 18:42 ` Sergey Fedorov
2016-02-08 13:11 ` Peter Maydell
2016-02-03 13:38 ` [Qemu-devel] [PATCH 3/7] target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR Peter Maydell
2016-02-05 13:43 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2016-02-06 12:17 ` [Qemu-devel] " Edgar E. Iglesias
2016-02-06 13:48 ` Peter Maydell
2016-02-06 16:03 ` Edgar E. Iglesias
2016-02-06 16:10 ` Edgar E. Iglesias
2016-02-03 13:38 ` [Qemu-devel] [PATCH 4/7] target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3 Peter Maydell
2016-02-05 14:09 ` Alex Bennée
2016-02-05 15:55 ` Peter Maydell
2016-02-06 18:43 ` Sergey Fedorov
2016-02-03 13:38 ` [Qemu-devel] [PATCH 5/7] target-arm: Add isread parameter to CPAccessFns Peter Maydell
2016-02-05 14:20 ` Alex Bennée
2016-02-05 14:29 ` Peter Maydell
2016-02-05 16:17 ` Alex Bennée
2016-02-05 16:27 ` Peter Maydell
2016-02-05 16:43 ` Alex Bennée
2016-02-06 16:16 ` Edgar E. Iglesias
2016-02-06 18:52 ` Sergey Fedorov
2016-02-03 13:38 ` [Qemu-devel] [PATCH 6/7] target-arm: Implement NSACR trapping behaviour Peter Maydell
2016-02-05 16:07 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2016-02-05 16:22 ` Peter Maydell
2016-02-06 16:42 ` [Qemu-devel] " Edgar E. Iglesias
2016-02-03 13:38 ` [Qemu-devel] [PATCH 7/7] target-arm: Enable EL3 for Cortex-A53 and Cortex-A57 Peter Maydell
2016-02-05 16:08 ` Alex Bennée
2016-02-06 16:43 ` Edgar E. Iglesias
2016-02-06 18:55 ` Sergey Fedorov
2016-02-08 13:18 ` [Qemu-devel] [Qemu-arm] [PATCH 0/7] Fix some more EL3 things and enable EL3 for AArch64 Peter Maydell
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