From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [Qemu-devel] [PATCH v2 33/68] target/arm: Convert RFE and SRS
Date: Mon, 19 Aug 2019 14:37:20 -0700 [thread overview]
Message-ID: <20190819213755.26175-34-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 150 ++++++++++++++---------------------
target/arm/a32-uncond.decode | 8 ++
target/arm/t32.decode | 12 +++
3 files changed, 81 insertions(+), 89 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b6d8b7be8c..e268c5168d 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9980,16 +9980,71 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
return true;
}
+/*
+ * Unconditional system instructions
+ */
+
+static bool trans_RFE(DisasContext *s, arg_RFE *a)
+{
+ int32_t offset;
+ TCGv_i32 addr, t1, t2;
+
+ if (IS_USER(s) || !ENABLE_ARCH_6) {
+ return false;
+ }
+
+ addr = load_reg(s, a->rn);
+
+ switch (a->pu) {
+ case 0: offset = -4; break; /* DA */
+ case 1: offset = 0; break; /* IA */
+ case 2: offset = -8; break; /* DB */
+ case 3: offset = 4; break; /* IB */
+ default:
+ g_assert_not_reached();
+ }
+ tcg_gen_addi_i32(addr, addr, offset);
+
+ /* Load PC into tmp and CPSR into tmp2. */
+ t1 = tcg_temp_new_i32();
+ gen_aa32_ld32u(s, t1, addr, get_mem_index(s));
+ tcg_gen_addi_i32(addr, addr, 4);
+ t2 = tcg_temp_new_i32();
+ gen_aa32_ld32u(s, t2, addr, get_mem_index(s));
+
+ if (a->w) {
+ /* Base writeback. */
+ switch (a->pu) {
+ case 0: offset = -8; break;
+ case 1: offset = 4; break;
+ case 2: offset = -4; break;
+ case 3: offset = 0; break;
+ }
+ tcg_gen_addi_i32(addr, addr, offset);
+ store_reg(s, a->rn, addr);
+ } else {
+ tcg_temp_free_i32(addr);
+ }
+ gen_rfe(s, t1, t2);
+ return true;
+}
+
+static bool trans_SRS(DisasContext *s, arg_SRS *a)
+{
+ if (!ENABLE_ARCH_6) {
+ return false;
+ }
+ gen_srs(s, a->mode, a->pu, a->w);
+ return true;
+}
+
/*
* Legacy decoder.
*/
static void disas_arm_insn(DisasContext *s, unsigned int insn)
{
- unsigned int cond, op1, i, rn;
- TCGv_i32 tmp;
- TCGv_i32 tmp2;
- TCGv_i32 addr;
+ unsigned int cond, op1;
/* M variants do not implement ARM mode; this must raise the INVSTATE
* UsageFault exception.
@@ -10108,52 +10163,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
default:
goto illegal_op;
}
- } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
- /* srs */
- ARCH(6);
- gen_srs(s, (insn & 0x1f), (insn >> 23) & 3, insn & (1 << 21));
- return;
- } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
- /* rfe */
- int32_t offset;
- if (IS_USER(s))
- goto illegal_op;
- ARCH(6);
- rn = (insn >> 16) & 0xf;
- addr = load_reg(s, rn);
- i = (insn >> 23) & 3;
- switch (i) {
- case 0: offset = -4; break; /* DA */
- case 1: offset = 0; break; /* IA */
- case 2: offset = -8; break; /* DB */
- case 3: offset = 4; break; /* IB */
- default: abort();
- }
- if (offset)
- tcg_gen_addi_i32(addr, addr, offset);
- /* Load PC into tmp and CPSR into tmp2. */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- tcg_gen_addi_i32(addr, addr, 4);
- tmp2 = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s));
- if (insn & (1 << 21)) {
- /* Base writeback. */
- switch (i) {
- case 0: offset = -8; break;
- case 1: offset = 4; break;
- case 2: offset = -4; break;
- case 3: offset = 0; break;
- default: abort();
- }
- if (offset)
- tcg_gen_addi_i32(addr, addr, offset);
- store_reg(s, rn, addr);
- } else {
- tcg_temp_free_i32(addr);
- }
- gen_rfe(s, tmp, tmp2);
- return;
} else if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
@@ -10316,7 +10325,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
uint32_t imm, offset;
uint32_t rd, rn, rm, rs;
TCGv_i32 tmp;
- TCGv_i32 tmp2;
TCGv_i32 addr;
int op;
@@ -10460,44 +10468,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op;
}
} else {
- /* Load/store multiple, RFE, SRS. */
- if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
- /* RFE, SRS: not available in user mode or on M profile */
- if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) {
- goto illegal_op;
- }
- if (insn & (1 << 20)) {
- /* rfe */
- addr = load_reg(s, rn);
- if ((insn & (1 << 24)) == 0)
- tcg_gen_addi_i32(addr, addr, -8);
- /* Load PC into tmp and CPSR into tmp2. */
- tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
- tcg_gen_addi_i32(addr, addr, 4);
- tmp2 = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s));
- if (insn & (1 << 21)) {
- /* Base writeback. */
- if (insn & (1 << 24)) {
- tcg_gen_addi_i32(addr, addr, 4);
- } else {
- tcg_gen_addi_i32(addr, addr, -4);
- }
- store_reg(s, rn, addr);
- } else {
- tcg_temp_free_i32(addr);
- }
- gen_rfe(s, tmp, tmp2);
- } else {
- /* srs */
- gen_srs(s, (insn & 0x1f), (insn & (1 << 24)) ? 1 : 2,
- insn & (1 << 21));
- }
- } else {
- /* Load/store multiple, in decodetree */
- goto illegal_op;
- }
+ /* Load/store multiple, RFE, SRS, in decodetree */
+ goto illegal_op;
}
break;
case 5:
diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode
index 573ac2cf8e..3b961233e5 100644
--- a/target/arm/a32-uncond.decode
+++ b/target/arm/a32-uncond.decode
@@ -29,3 +29,11 @@
%imm24h 0:s24 24:1 !function=times_2
BLX_i 1111 101 . ........................ &i imm=%imm24h
+
+# System Instructions
+
+&rfe rn w pu
+&srs mode w pu
+
+RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe
+SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index ebc92f2c28..c8a8aeceee 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -582,6 +582,18 @@ STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1
LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0
LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1
+&rfe !extern rn w pu
+@rfe .... .... .. w:1 . rn:4 ................ &rfe
+
+RFE 1110 1000 00.1 .... 1100000000000000 @rfe pu=2
+RFE 1110 1001 10.1 .... 1100000000000000 @rfe pu=1
+
+&srs !extern mode w pu
+@srs .... .... .. w:1 . .... ........... mode:5 &srs
+
+SRS 1110 1000 00.0 1101 1100 0000 000. .... @srs pu=2
+SRS 1110 1001 10.0 1101 1100 0000 000. .... @srs pu=1
+
# Branches
%imm24 26:s1 13:1 11:1 16:10 0:11 !function=t32_branch24
--
2.17.1
next prev parent reply other threads:[~2019-08-19 22:07 UTC|newest]
Thread overview: 167+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-19 21:36 [Qemu-devel] [PATCH v2 00/68] target/arm: Convert aa32 base isa to decodetree Richard Henderson
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 01/68] target/arm: Use store_reg_from_load in thumb2 code Richard Henderson
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 02/68] target/arm: Add stubs for aa32 decodetree Richard Henderson
2019-08-21 13:06 ` Philippe Mathieu-Daudé
2019-08-23 12:16 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 03/68] target/arm: Convert Data Processing (register) Richard Henderson
2019-08-22 16:00 ` Peter Maydell
2019-08-22 17:21 ` Richard Henderson
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 04/68] target/arm: Convert Data Processing (reg-shifted-reg) Richard Henderson
2019-08-23 12:17 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 05/68] target/arm: Convert Data Processing (immediate) Richard Henderson
2019-08-23 12:18 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 06/68] target/arm: Convert multiply and multiply accumulate Richard Henderson
2019-08-23 12:18 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 07/68] target/arm: Simplify UMAAL Richard Henderson
2019-08-23 12:20 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 08/68] target/arm: Convert Saturating addition and subtraction Richard Henderson
2019-08-21 13:15 ` Philippe Mathieu-Daudé
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 09/68] target/arm: Convert Halfword multiply and multiply accumulate Richard Henderson
2019-08-23 12:20 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 10/68] target/arm: Simplify op_smlaxxx for SMLAL* Richard Henderson
2019-08-23 12:21 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 11/68] target/arm: Simplify op_smlawx for SMLAW* Richard Henderson
2019-08-23 12:21 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 12/68] target/arm: Convert MSR (immediate) and hints Richard Henderson
2019-08-23 12:22 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 13/68] target/arm: Convert MRS/MSR (banked, register) Richard Henderson
2019-08-23 12:23 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 14/68] target/arm: Convert Cyclic Redundancy Check Richard Henderson
2019-08-23 12:23 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (register) Richard Henderson
2019-08-23 11:49 ` Peter Maydell
2019-08-23 14:22 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 16/68] target/arm: Convert CLZ Richard Henderson
2019-08-23 11:52 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 17/68] target/arm: Convert ERET Richard Henderson
2019-08-23 12:25 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 18/68] target/arm: Convert the rest of A32 Miscelaneous instructions Richard Henderson
2019-08-23 12:03 ` Peter Maydell
2019-08-23 14:33 ` Richard Henderson
2019-08-27 10:32 ` Peter Maydell
2019-08-27 20:01 ` Richard Henderson
2019-08-27 22:29 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 19/68] target/arm: Convert T32 ADDW/SUBW Richard Henderson
2019-08-23 13:04 ` Peter Maydell
2019-08-23 14:45 ` Richard Henderson
2019-08-23 14:47 ` Peter Maydell
2019-08-23 14:57 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 20/68] target/arm: Convert load/store (register, immediate, literal) Richard Henderson
2019-08-23 14:54 ` Peter Maydell
2019-08-23 16:24 ` Richard Henderson
2019-08-27 12:27 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 21/68] target/arm: Convert Synchronization primitives Richard Henderson
2019-08-23 15:28 ` Peter Maydell
2019-08-23 16:28 ` Richard Henderson
2019-08-27 10:44 ` Peter Maydell
2019-08-27 10:46 ` Peter Maydell
2019-08-27 11:10 ` Peter Maydell
2019-08-27 19:35 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 22/68] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF Richard Henderson
2019-08-23 15:39 ` Peter Maydell
2019-08-23 16:30 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 23/68] target/arm: Convert Parallel addition and subtraction Richard Henderson
2019-08-23 15:53 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 24/68] target/arm: Convert Packing, unpacking, saturation, and reversal Richard Henderson
2019-08-23 16:46 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 25/68] target/arm: Convert Signed multiply, signed and unsigned divide Richard Henderson
2019-08-23 17:00 ` Peter Maydell
2019-08-23 17:15 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 26/68] target/arm: Convert MOVW, MOVT Richard Henderson
2019-08-23 17:05 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 27/68] target/arm: Convert LDM, STM Richard Henderson
2019-08-23 17:27 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 28/68] target/arm: Diagnose writeback register in list for LDM for v7 Richard Henderson
2019-08-23 17:29 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 29/68] target/arm: Diagnose too few registers in list for LDM/STM Richard Henderson
2019-08-23 17:30 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 30/68] target/arm: Diagnose base == pc " Richard Henderson
2019-08-23 17:31 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 31/68] target/arm: Convert B, BL, BLX (immediate) Richard Henderson
2019-08-23 17:53 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 32/68] target/arm: Convert SVC Richard Henderson
2019-08-21 13:21 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` Richard Henderson [this message]
2019-08-25 15:28 ` [Qemu-devel] [PATCH v2 33/68] target/arm: Convert RFE and SRS Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 34/68] target/arm: Convert Clear-Exclusive, Barriers Richard Henderson
2019-08-25 15:52 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 35/68] target/arm: Convert CPS (privileged) Richard Henderson
2019-08-25 16:20 ` Peter Maydell
2019-08-25 17:28 ` Richard Henderson
2019-08-25 17:40 ` Richard Henderson
2019-08-25 20:43 ` Peter Maydell
2019-08-26 1:10 ` Richard Henderson
2019-08-26 1:36 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 36/68] target/arm: Convert SETEND Richard Henderson
2019-08-21 13:22 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 37/68] target/arm: Convert PLI, PLD, PLDW Richard Henderson
2019-08-21 13:23 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 38/68] target/arm: Convert Unallocated memory hint Richard Henderson
2019-08-21 13:24 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 39/68] target/arm: Convert Table Branch Richard Henderson
2019-08-25 16:27 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 40/68] target/arm: Convert SG Richard Henderson
2019-08-25 16:28 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 41/68] target/arm: Convert TT Richard Henderson
2019-08-25 16:33 ` Peter Maydell
2019-08-27 11:09 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 42/68] target/arm: Simplify disas_thumb2_insn Richard Henderson
2019-08-25 16:35 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 43/68] target/arm: Simplify disas_arm_insn Richard Henderson
2019-08-25 16:36 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 44/68] target/arm: Add skeleton for T16 decodetree Richard Henderson
2019-08-21 13:25 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 45/68] target/arm: Convert T16 data-processing (two low regs) Richard Henderson
2019-08-25 21:06 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 46/68] target/arm: Convert T16 load/store (register offset) Richard Henderson
2019-08-25 21:13 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 47/68] target/arm: Convert T16 load/store (immediate offset) Richard Henderson
2019-08-25 21:22 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 48/68] target/arm: Convert T16 add pc/sp (immediate) Richard Henderson
2019-08-25 21:24 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 49/68] target/arm: Convert T16 load/store multiple Richard Henderson
2019-08-25 21:29 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 50/68] target/arm: Convert T16 add/sub (3 low, 2 low and imm) Richard Henderson
2019-08-25 21:33 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 51/68] target/arm: Convert T16 one low register and immediate Richard Henderson
2019-08-25 21:34 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 52/68] target/arm: Convert T16 branch and exchange Richard Henderson
2019-08-25 21:40 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 53/68] target/arm: Convert T16 add, compare, move (two high registers) Richard Henderson
2019-08-25 21:43 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 54/68] target/arm: Convert T16 adjust sp (immediate) Richard Henderson
2019-08-26 19:00 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 55/68] target/arm: Convert T16, extract Richard Henderson
2019-08-26 19:08 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 56/68] target/arm: Convert T16, Change processor state Richard Henderson
2019-08-26 19:25 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 57/68] target/arm: Convert T16, Reverse bytes Richard Henderson
2019-08-26 19:35 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 58/68] target/arm: Convert T16, nop hints Richard Henderson
2019-08-26 19:37 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 59/68] target/arm: Split gen_nop_hint Richard Henderson
2019-08-26 19:40 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 60/68] target/arm: Convert T16, push and pop Richard Henderson
2019-08-26 19:44 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 61/68] target/arm: Convert T16, Conditional branches, Supervisor call Richard Henderson
2019-08-26 19:52 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 62/68] target/arm: Convert T16, Miscellaneous 16-bit instructions Richard Henderson
2019-08-26 20:38 ` Peter Maydell
2019-08-26 23:47 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 63/68] target/arm: Convert T16, shift immediate Richard Henderson
2019-08-27 9:09 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 64/68] target/arm: Convert T16, load (literal) Richard Henderson
2019-08-27 9:11 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 65/68] target/arm: Convert T16, Unconditional branch Richard Henderson
2019-08-27 9:14 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 66/68] target/arm: Convert T16, long branches Richard Henderson
2019-08-27 9:34 ` Peter Maydell
2019-08-28 0:07 ` Richard Henderson
2019-09-03 8:23 ` Peter Maydell
2019-09-03 9:40 ` Aleksandar Markovic
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 67/68] target/arm: Clean up disas_thumb_insn Richard Henderson
2019-08-27 9:35 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 68/68] target/arm: Inline gen_bx_im into callers Richard Henderson
2019-08-27 9:39 ` Peter Maydell
2019-08-19 22:47 ` [Qemu-devel] [PATCH v2 00/68] target/arm: Convert aa32 base isa to decodetree no-reply
2019-08-27 12:28 ` Peter Maydell
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