From: David Hildenbrand <david@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-s390x@nongnu.org, Cornelia Huck <cohuck@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Thomas Huth <thuth@redhat.com>,
David Hildenbrand <david@redhat.com>
Subject: [PULL 07/31] s390x/mmu: Convert to non-recursive page table walk
Date: Thu, 10 Oct 2019 13:33:32 +0200 [thread overview]
Message-ID: <20191010113356.5017-8-david@redhat.com> (raw)
In-Reply-To: <20191010113356.5017-1-david@redhat.com>
A non-recursive implementation allows to make better use of the
branch predictor, avoids function calls, and makes the implementation of
new features only for a subset of region table levels easier.
We can now directly compare our implementation to the KVM gaccess
implementation in arch/s390/kvm/gaccess.c:guest_translate().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/mmu_helper.c | 208 ++++++++++++++++++++------------------
1 file changed, 108 insertions(+), 100 deletions(-)
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
index a114fb1628..dc33c63b1d 100644
--- a/target/s390x/mmu_helper.c
+++ b/target/s390x/mmu_helper.c
@@ -114,107 +114,16 @@ static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr,
return true;
}
-/* Decode page table entry (normal 4KB page) */
-static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr,
- uint64_t asc, uint64_t pt_entry,
- target_ulong *raddr, int *flags, int rw, bool exc)
-{
- if (pt_entry & PAGE_ENTRY_I) {
- return PGM_PAGE_TRANS;
- }
- if (pt_entry & PAGE_ENTRY_0) {
- return PGM_TRANS_SPEC;
- }
- if (pt_entry & PAGE_ENTRY_P) {
- *flags &= ~PAGE_WRITE;
- }
-
- *raddr = pt_entry & TARGET_PAGE_MASK;
- return 0;
-}
-
-/* Decode segment table entry */
-static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
- uint64_t asc, uint64_t st_entry,
- target_ulong *raddr, int *flags, int rw,
- bool exc)
-{
- uint64_t origin, offs, pt_entry;
-
- if (st_entry & SEGMENT_ENTRY_P) {
- *flags &= ~PAGE_WRITE;
- }
-
- if ((st_entry & SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {
- /* Decode EDAT1 segment frame absolute address (1MB page) */
- *raddr = (st_entry & SEGMENT_ENTRY_SFAA) |
- (vaddr & ~SEGMENT_ENTRY_SFAA);
- return 0;
- }
-
- /* Look up 4KB page entry */
- origin = st_entry & SEGMENT_ENTRY_ORIGIN;
- offs = VADDR_PAGE_TX(vaddr) * 8;
- if (!read_table_entry(env, origin + offs, &pt_entry)) {
- return PGM_ADDRESSING;
- }
- return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw, exc);
-}
-
-/* Decode region table entries */
-static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
- uint64_t asc, uint64_t entry, int level,
- target_ulong *raddr, int *flags, int rw,
- bool exc)
-{
- uint64_t origin, offs, new_entry;
- const int pchks[4] = {
- PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS,
- PGM_REG_SEC_TRANS, PGM_REG_FIRST_TRANS
- };
-
- origin = entry & REGION_ENTRY_ORIGIN;
- offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8;
-
- if (!read_table_entry(env, origin + offs, &new_entry)) {
- return PGM_ADDRESSING;
- }
-
- if (new_entry & REGION_ENTRY_I) {
- return pchks[level / 4];
- }
-
- if ((new_entry & REGION_ENTRY_TT) != level) {
- return PGM_TRANS_SPEC;
- }
-
- if (level == ASCE_TYPE_SEGMENT) {
- return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, flags,
- rw, exc);
- }
-
- /* Check region table offset and length */
- offs = (vaddr >> (28 + 11 * (level - 4) / 4)) & 3;
- if (offs < ((new_entry & REGION_ENTRY_TF) >> 6)
- || offs > (new_entry & REGION_ENTRY_TL)) {
- return pchks[level / 4 - 1];
- }
-
- if ((env->cregs[0] & CR0_EDAT) && (new_entry & REGION_ENTRY_P)) {
- *flags &= ~PAGE_WRITE;
- }
-
- /* yet another region */
- return mmu_translate_region(env, vaddr, asc, new_entry, level - 4,
- raddr, flags, rw, exc);
-}
-
static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
uint64_t asc, uint64_t asce, target_ulong *raddr,
int *flags, int rw, bool exc)
{
+ const bool edat1 = (env->cregs[0] & CR0_EDAT) &&
+ s390_has_feat(S390_FEAT_EDAT);
const int asce_tl = asce & ASCE_TABLE_LENGTH;
- int level;
+ const int asce_p = asce & ASCE_PRIVATE_SPACE;
+ hwaddr gaddr = asce & ASCE_ORIGIN;
+ uint64_t entry;
if (asce & ASCE_REAL_SPACE) {
/* direct mapping */
@@ -222,12 +131,12 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
return 0;
}
- level = asce & ASCE_TYPE_MASK;
- switch (level) {
+ switch (asce & ASCE_TYPE_MASK) {
case ASCE_TYPE_REGION1:
if (VADDR_REGION1_TL(vaddr) > asce_tl) {
return PGM_REG_FIRST_TRANS;
}
+ gaddr += VADDR_REGION1_TX(vaddr) * 8;
break;
case ASCE_TYPE_REGION2:
if (VADDR_REGION1_TX(vaddr)) {
@@ -236,6 +145,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
if (VADDR_REGION2_TL(vaddr) > asce_tl) {
return PGM_REG_SEC_TRANS;
}
+ gaddr += VADDR_REGION2_TX(vaddr) * 8;
break;
case ASCE_TYPE_REGION3:
if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr)) {
@@ -244,6 +154,7 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
if (VADDR_REGION3_TL(vaddr) > asce_tl) {
return PGM_REG_THIRD_TRANS;
}
+ gaddr += VADDR_REGION3_TX(vaddr) * 8;
break;
case ASCE_TYPE_SEGMENT:
if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr) ||
@@ -253,11 +164,108 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
if (VADDR_SEGMENT_TL(vaddr) > asce_tl) {
return PGM_SEGMENT_TRANS;
}
+ gaddr += VADDR_SEGMENT_TX(vaddr) * 8;
+ break;
+ }
+
+ switch (asce & ASCE_TYPE_MASK) {
+ case ASCE_TYPE_REGION1:
+ if (!read_table_entry(env, gaddr, &entry)) {
+ return PGM_ADDRESSING;
+ }
+ if (entry & REGION_ENTRY_I) {
+ return PGM_REG_FIRST_TRANS;
+ }
+ if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION1) {
+ return PGM_TRANS_SPEC;
+ }
+ if (VADDR_REGION2_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
+ VADDR_REGION2_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
+ return PGM_REG_SEC_TRANS;
+ }
+ if (edat1 && (entry & REGION_ENTRY_P)) {
+ *flags &= ~PAGE_WRITE;
+ }
+ gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION2_TX(vaddr) * 8;
+ /* fall through */
+ case ASCE_TYPE_REGION2:
+ if (!read_table_entry(env, gaddr, &entry)) {
+ return PGM_ADDRESSING;
+ }
+ if (entry & REGION_ENTRY_I) {
+ return PGM_REG_SEC_TRANS;
+ }
+ if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION2) {
+ return PGM_TRANS_SPEC;
+ }
+ if (VADDR_REGION3_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
+ VADDR_REGION3_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
+ return PGM_REG_THIRD_TRANS;
+ }
+ if (edat1 && (entry & REGION_ENTRY_P)) {
+ *flags &= ~PAGE_WRITE;
+ }
+ gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION3_TX(vaddr) * 8;
+ /* fall through */
+ case ASCE_TYPE_REGION3:
+ if (!read_table_entry(env, gaddr, &entry)) {
+ return PGM_ADDRESSING;
+ }
+ if (entry & REGION_ENTRY_I) {
+ return PGM_REG_THIRD_TRANS;
+ }
+ if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION3) {
+ return PGM_TRANS_SPEC;
+ }
+ if (VADDR_SEGMENT_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
+ VADDR_SEGMENT_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
+ return PGM_SEGMENT_TRANS;
+ }
+ if (edat1 && (entry & REGION_ENTRY_P)) {
+ *flags &= ~PAGE_WRITE;
+ }
+ gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_SEGMENT_TX(vaddr) * 8;
+ /* fall through */
+ case ASCE_TYPE_SEGMENT:
+ if (!read_table_entry(env, gaddr, &entry)) {
+ return PGM_ADDRESSING;
+ }
+ if (entry & SEGMENT_ENTRY_I) {
+ return PGM_SEGMENT_TRANS;
+ }
+ if ((entry & SEGMENT_ENTRY_TT) != SEGMENT_ENTRY_TT_SEGMENT) {
+ return PGM_TRANS_SPEC;
+ }
+ if ((entry & SEGMENT_ENTRY_CS) && asce_p) {
+ return PGM_TRANS_SPEC;
+ }
+ if (entry & SEGMENT_ENTRY_P) {
+ *flags &= ~PAGE_WRITE;
+ }
+ if (edat1 && (entry & SEGMENT_ENTRY_FC)) {
+ *raddr = (entry & SEGMENT_ENTRY_SFAA) |
+ (vaddr & ~SEGMENT_ENTRY_SFAA);
+ return 0;
+ }
+ gaddr = (entry & SEGMENT_ENTRY_ORIGIN) + VADDR_PAGE_TX(vaddr) * 8;
break;
}
- return mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags, rw,
- exc);
+ if (!read_table_entry(env, gaddr, &entry)) {
+ return PGM_ADDRESSING;
+ }
+ if (entry & PAGE_ENTRY_I) {
+ return PGM_PAGE_TRANS;
+ }
+ if (entry & PAGE_ENTRY_0) {
+ return PGM_TRANS_SPEC;
+ }
+ if (entry & PAGE_ENTRY_P) {
+ *flags &= ~PAGE_WRITE;
+ }
+
+ *raddr = entry & TARGET_PAGE_MASK;
+ return 0;
}
static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
--
2.21.0
next prev parent reply other threads:[~2019-10-10 11:43 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-10 11:33 [PULL 00/31] s390x/tcg update David Hildenbrand
2019-10-10 11:33 ` [PULL 01/31] s390x/mmu: Drop debug logging from MMU code David Hildenbrand
2019-10-10 11:33 ` [PULL 02/31] s390x/mmu: Move DAT protection handling out of mmu_translate_asce() David Hildenbrand
2019-10-10 11:33 ` [PULL 03/31] s390x/mmu: Inject DAT exceptions from a single place David Hildenbrand
2019-10-10 11:33 ` [PULL 04/31] s390x/mmu: Inject PGM_ADDRESSING on bogus table addresses David Hildenbrand
2019-10-10 11:33 ` [PULL 05/31] s390x/mmu: Use TARGET_PAGE_MASK in mmu_translate_pte() David Hildenbrand
2019-10-10 11:33 ` [PULL 06/31] s390x/mmu: DAT table definition overhaul David Hildenbrand
2019-10-10 11:33 ` David Hildenbrand [this message]
2019-10-10 11:33 ` [PULL 08/31] s390x/mmu: Add EDAT2 translation support David Hildenbrand
2019-10-10 11:33 ` [PULL 09/31] s390x/mmu: Implement ESOP-2 and access-exception-fetch/store-indication facility David Hildenbrand
2019-10-10 11:33 ` [PULL 10/31] s390x/mmu: Implement Instruction-Execution-Protection Facility David Hildenbrand
2019-10-10 11:33 ` [PULL 11/31] s390x/cpumodel: Prepare for changes of QEMU model David Hildenbrand
2019-10-10 11:33 ` [PULL 12/31] s390x/cpumodel: Add new TCG features to QEMU cpu model David Hildenbrand
2019-10-10 11:33 ` [PULL 13/31] target/s390x: Add ilen to unwind data David Hildenbrand
2019-10-10 11:33 ` [PULL 14/31] target/s390x: Remove ilen parameter from tcg_s390_program_interrupt David Hildenbrand
2019-10-10 11:33 ` [PULL 15/31] target/s390x: Remove ilen parameter from s390_program_interrupt David Hildenbrand
2019-10-10 11:33 ` [PULL 16/31] target/s390x: Use tcg_s390_program_interrupt in TCG helpers David Hildenbrand
2019-10-10 11:33 ` [PULL 17/31] target/s390x: Push trigger_pgm_exception lower in s390_cpu_tlb_fill David Hildenbrand
2019-10-10 11:33 ` [PULL 18/31] target/s390x: Handle tec " David Hildenbrand
2019-10-10 11:33 ` [PULL 19/31] target/s390x: Return exception from mmu_translate_real David Hildenbrand
2019-10-17 11:57 ` Peter Maydell
2019-10-17 12:05 ` Peter Maydell
2019-10-17 12:13 ` David Hildenbrand
2019-10-10 11:33 ` [PULL 20/31] target/s390x: Remove exc argument to mmu_translate_asce David Hildenbrand
2019-10-10 11:33 ` [PULL 21/31] target/s390x: Return exception from mmu_translate David Hildenbrand
2019-10-10 11:33 ` [PULL 22/31] target/s390x: Return exception from translate_pages David Hildenbrand
2019-10-10 11:33 ` [PULL 23/31] target/s390x: Remove fail variable from s390_cpu_tlb_fill David Hildenbrand
2019-10-10 11:33 ` [PULL 24/31] target/s390x: Simplify helper_lra David Hildenbrand
2019-10-10 11:33 ` [PULL 25/31] target/s390x: Rely on unwinding in s390_cpu_tlb_fill David Hildenbrand
2019-10-10 11:33 ` [PULL 26/31] target/s390x: Rely on unwinding in s390_cpu_virt_mem_rw David Hildenbrand
2019-10-10 11:33 ` [PULL 27/31] target/s390x: Remove ILEN_AUTO David Hildenbrand
2019-10-10 11:33 ` [PULL 28/31] target/s390x: Remove ilen argument from trigger_access_exception David Hildenbrand
2019-10-10 11:33 ` [PULL 29/31] target/s390x: Remove ilen argument from trigger_pgm_exception David Hildenbrand
2019-10-10 11:33 ` [PULL 30/31] target/s390x: Remove ILEN_UNWIND David Hildenbrand
2019-10-10 11:33 ` [PULL 31/31] s390x/tcg: MVCL: Exit to main loop if requested David Hildenbrand
2019-10-10 12:33 ` [PULL 00/31] s390x/tcg update no-reply
2019-10-10 13:11 ` David Hildenbrand
2019-10-14 11:26 ` Peter Maydell
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