From: "Alex Bennée" <alex.bennee@linaro.org>
To: peter.maydell@linaro.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
qemu-devel@nongnu.org
Subject: [PULL v2 66/73] tests/plugin: add instruction execution breakdown
Date: Fri, 25 Oct 2019 07:37:06 +0100 [thread overview]
Message-ID: <20191025063713.23374-67-alex.bennee@linaro.org> (raw)
In-Reply-To: <20191025063713.23374-1-alex.bennee@linaro.org>
This gives a break down of instruction classes and individual
instruction types.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
diff --git a/tests/plugin/Makefile b/tests/plugin/Makefile
index e74940eaac5..3656429d46b 100644
--- a/tests/plugin/Makefile
+++ b/tests/plugin/Makefile
@@ -11,6 +11,7 @@ NAMES += empty
NAMES += insn
NAMES += mem
NAMES += hotblocks
+NAMES += howvec
SONAMES := $(addsuffix .so,$(addprefix lib,$(NAMES)))
diff --git a/tests/plugin/howvec.c b/tests/plugin/howvec.c
new file mode 100644
index 00000000000..58fa675e348
--- /dev/null
+++ b/tests/plugin/howvec.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright (C) 2019, Alex Bennée <alex.bennee@linaro.org>
+ *
+ * How vectorised is this code?
+ *
+ * Attempt to measure the amount of vectorisation that has been done
+ * on some code by counting classes of instruction.
+ *
+ * License: GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include <inttypes.h>
+#include <assert.h>
+#include <stdlib.h>
+#include <inttypes.h>
+#include <string.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <glib.h>
+
+#include <qemu-plugin.h>
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+typedef enum {
+ COUNT_CLASS,
+ COUNT_INDIVIDUAL,
+ COUNT_NONE
+} CountType;
+
+static int limit = 50;
+static bool do_inline;
+static bool verbose;
+
+static GMutex lock;
+static GHashTable *insns;
+
+typedef struct {
+ const char *class;
+ const char *opt;
+ uint32_t mask;
+ uint32_t pattern;
+ CountType what;
+ uint64_t count;
+} InsnClassExecCount;
+
+typedef struct {
+ char *insn;
+ uint32_t opcode;
+ uint64_t count;
+ InsnClassExecCount *class;
+} InsnExecCount;
+
+/*
+ * Matchers for classes of instructions, order is important.
+ *
+ * Your most precise match must be before looser matches. If no match
+ * is found in the table we can create an individual entry.
+ *
+ * 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0
+ */
+static InsnClassExecCount aarch64_insn_classes[] = {
+ /* "Reserved"" */
+ { " UDEF", "udef", 0xffff0000, 0x00000000, COUNT_NONE},
+ { " SVE", "sve", 0x1e000000, 0x04000000, COUNT_CLASS},
+ { "Reserved", "res", 0x1e000000, 0x00000000, COUNT_CLASS},
+ /* Data Processing Immediate */
+ { " PCrel addr", "pcrel", 0x1f000000, 0x10000000, COUNT_CLASS},
+ { " Add/Sub (imm,tags)","asit", 0x1f800000, 0x11800000, COUNT_CLASS},
+ { " Add/Sub (imm)", "asi", 0x1f000000, 0x11000000, COUNT_CLASS},
+ { " Logical (imm)", "logi", 0x1f800000, 0x12000000, COUNT_CLASS},
+ { " Move Wide (imm)", "movwi", 0x1f800000, 0x12800000, COUNT_CLASS},
+ { " Bitfield", "bitf", 0x1f800000, 0x13000000, COUNT_CLASS},
+ { " Extract", "extr", 0x1f800000, 0x13800000, COUNT_CLASS},
+ { "Data Proc Imm", "dpri", 0x1c000000, 0x10000000, COUNT_CLASS},
+ /* Branches */
+ { " Cond Branch (imm)", "cndb", 0xfe000000, 0x54000000, COUNT_CLASS},
+ { " Exception Gen", "excp", 0xff000000, 0xd4000000, COUNT_CLASS},
+ { " NOP", "nop", 0xffffffff, 0xd503201f, COUNT_NONE},
+ { " Hints", "hint", 0xfffff000, 0xd5032000, COUNT_CLASS},
+ { " Barriers", "barr", 0xfffff000, 0xd5033000, COUNT_CLASS},
+ { " PSTATE", "psta", 0xfff8f000, 0xd5004000, COUNT_CLASS},
+ { " System Insn", "sins", 0xffd80000, 0xd5080000, COUNT_CLASS},
+ { " System Reg", "sreg", 0xffd00000, 0xd5100000, COUNT_CLASS},
+ { " Branch (reg)", "breg", 0xfe000000, 0xd6000000, COUNT_CLASS},
+ { " Branch (imm)", "bimm", 0x7c000000, 0x14000000, COUNT_CLASS},
+ { " Cmp & Branch", "cmpb", 0x7e000000, 0x34000000, COUNT_CLASS},
+ { " Tst & Branch", "tstb", 0x7e000000, 0x36000000, COUNT_CLASS},
+ { "Branches", "branch", 0x1c000000, 0x14000000, COUNT_CLASS},
+ /* Loads and Stores */
+ { " AdvSimd ldstmult", "advlsm", 0xbfbf0000, 0x0c000000, COUNT_CLASS},
+ { " AdvSimd ldstmult++","advlsmp",0xbfb00000, 0x0c800000, COUNT_CLASS},
+ { " AdvSimd ldst", "advlss", 0xbf9f0000, 0x0d000000, COUNT_CLASS},
+ { " AdvSimd ldst++", "advlssp",0xbf800000, 0x0d800000, COUNT_CLASS},
+ { " ldst excl", "ldstx", 0x3f000000, 0x08000000, COUNT_CLASS},
+ { " Prefetch", "prfm", 0xff000000, 0xd8000000, COUNT_CLASS},
+ { " Load Reg (lit)", "ldlit", 0x1b000000, 0x18000000, COUNT_CLASS},
+ { " ldst noalloc pair", "ldstnap",0x3b800000, 0x28000000, COUNT_CLASS},
+ { " ldst pair", "ldstp", 0x38000000, 0x28000000, COUNT_CLASS},
+ { " ldst reg", "ldstr", 0x3b200000, 0x38000000, COUNT_CLASS},
+ { " Atomic ldst", "atomic", 0x3b200c00, 0x38200000, COUNT_CLASS},
+ { " ldst reg (reg off)","ldstro", 0x3b200b00, 0x38200800, COUNT_CLASS},
+ { " ldst reg (pac)", "ldstpa", 0x3b200200, 0x38200800, COUNT_CLASS},
+ { " ldst reg (imm)", "ldsti", 0x3b000000, 0x39000000, COUNT_CLASS},
+ { "Loads & Stores", "ldst", 0x0a000000, 0x08000000, COUNT_CLASS},
+ /* Data Processing Register */
+ { "Data Proc Reg", "dprr", 0x0e000000, 0x0a000000, COUNT_CLASS},
+ /* Scalar FP */
+ { "Scalar FP ", "fpsimd", 0x0e000000, 0x0e000000, COUNT_CLASS},
+ /* Unclassified */
+ { "Unclassified", "unclas", 0x00000000, 0x00000000, COUNT_CLASS},
+};
+
+static InsnClassExecCount sparc32_insn_classes[] = {
+ { "Call", "call", 0xc0000000, 0x40000000, COUNT_CLASS},
+ { "Branch ICond", "bcc", 0xc1c00000, 0x00800000, COUNT_CLASS},
+ { "Branch Fcond", "fbcc", 0xc1c00000, 0x01800000, COUNT_CLASS},
+ { "SetHi", "sethi", 0xc1c00000, 0x01000000, COUNT_CLASS},
+ { "FPU ALU", "fpu", 0xc1f00000, 0x81a00000, COUNT_CLASS},
+ { "ALU", "alu", 0xc0000000, 0x80000000, COUNT_CLASS},
+ { "Load/Store", "ldst", 0xc0000000, 0xc0000000, COUNT_CLASS},
+ /* Unclassified */
+ { "Unclassified", "unclas", 0x00000000, 0x00000000, COUNT_INDIVIDUAL},
+};
+
+static InsnClassExecCount sparc64_insn_classes[] = {
+ { "SetHi & Branches", "op0", 0xc0000000, 0x00000000, COUNT_CLASS},
+ { "Call", "op1", 0xc0000000, 0x40000000, COUNT_CLASS},
+ { "Arith/Logical/Move", "op2", 0xc0000000, 0x80000000, COUNT_CLASS},
+ { "Arith/Logical/Move", "op3", 0xc0000000, 0xc0000000, COUNT_CLASS},
+ /* Unclassified */
+ { "Unclassified", "unclas", 0x00000000, 0x00000000, COUNT_INDIVIDUAL},
+};
+
+/* Default matcher for currently unclassified architectures */
+static InsnClassExecCount default_insn_classes[] = {
+ { "Unclassified", "unclas", 0x00000000, 0x00000000, COUNT_INDIVIDUAL},
+};
+
+typedef struct {
+ const char *qemu_target;
+ InsnClassExecCount *table;
+ int table_sz;
+} ClassSelector;
+
+static ClassSelector class_tables[] =
+{
+ { "aarch64", aarch64_insn_classes, ARRAY_SIZE(aarch64_insn_classes) },
+ { "sparc", sparc32_insn_classes, ARRAY_SIZE(sparc32_insn_classes) },
+ { "sparc64", sparc64_insn_classes, ARRAY_SIZE(sparc64_insn_classes) },
+ { NULL, default_insn_classes, ARRAY_SIZE(default_insn_classes) },
+};
+
+static InsnClassExecCount *class_table;
+static int class_table_sz;
+
+static gint cmp_exec_count(gconstpointer a, gconstpointer b)
+{
+ InsnExecCount *ea = (InsnExecCount *) a;
+ InsnExecCount *eb = (InsnExecCount *) b;
+ return ea->count > eb->count ? -1 : 1;
+}
+
+static void plugin_exit(qemu_plugin_id_t id, void *p)
+{
+ g_autoptr(GString) report = g_string_new("Instruction Classes:\n");
+ int i;
+ GList *counts;
+ InsnClassExecCount *class = NULL;
+
+ for (i = 0; i < class_table_sz; i++) {
+ class = &class_table[i];
+ switch (class->what) {
+ case COUNT_CLASS:
+ if (class->count || verbose) {
+ g_string_append_printf(report, "Class: %-24s\t(%ld hits)\n",
+ class->class,
+ class->count);
+ }
+ break;
+ case COUNT_INDIVIDUAL:
+ g_string_append_printf(report, "Class: %-24s\tcounted individually\n",
+ class->class);
+ break;
+ case COUNT_NONE:
+ g_string_append_printf(report, "Class: %-24s\tnot counted\n",
+ class->class);
+ break;
+ default:
+ break;
+ }
+ }
+
+ counts = g_hash_table_get_values(insns);
+ if (counts && g_list_next(counts)) {
+ GList *it;
+
+ g_string_append_printf(report,"Individual Instructions:\n");
+
+ it = g_list_sort(counts, cmp_exec_count);
+
+ for (i = 0; i < limit && it->next; i++, it = it->next) {
+ InsnExecCount *rec = (InsnExecCount *) it->data;
+ g_string_append_printf(report, "Instr: %-24s\t(%ld hits)\t(op=%#08x/%s)\n",
+ rec->insn,
+ rec->count,
+ rec->opcode,
+ rec->class ?
+ rec->class->class : "un-categorised");
+ }
+ g_list_free(it);
+ }
+
+ qemu_plugin_outs(report->str);
+}
+
+static void plugin_init(void)
+{
+ insns = g_hash_table_new(NULL, g_direct_equal);
+}
+
+static void vcpu_insn_exec_before(unsigned int cpu_index, void *udata)
+{
+ uint64_t *count = (uint64_t *) udata;
+ (*count)++;
+}
+
+static uint64_t * find_counter(struct qemu_plugin_insn *insn)
+{
+ int i;
+ uint64_t *cnt = NULL;
+ uint32_t opcode;
+ InsnClassExecCount *class = NULL;
+
+ /*
+ * We only match the first 32 bits of the instruction which is
+ * fine for most RISCs but a bit limiting for CISC architectures.
+ * They would probably benefit from a more tailored plugin.
+ * However we can fall back to individual instruction counting.
+ */
+ opcode = *((uint32_t *)qemu_plugin_insn_data(insn));
+
+ for (i = 0; !cnt && i < class_table_sz; i++) {
+ class = &class_table[i];
+ uint32_t masked_bits = opcode & class->mask;
+ if (masked_bits == class->pattern) {
+ break;
+ }
+ }
+
+ g_assert(class);
+
+ switch (class->what) {
+ case COUNT_NONE:
+ return NULL;
+ case COUNT_CLASS:
+ return &class->count;
+ case COUNT_INDIVIDUAL:
+ {
+ InsnExecCount *icount;
+
+ g_mutex_lock(&lock);
+ icount = (InsnExecCount *) g_hash_table_lookup(insns,
+ GUINT_TO_POINTER(opcode));
+
+ if (!icount) {
+ icount = g_new0(InsnExecCount, 1);
+ icount->opcode = opcode;
+ icount->insn = qemu_plugin_insn_disas(insn);
+ icount->class = class;
+
+ g_hash_table_insert(insns, GUINT_TO_POINTER(opcode),
+ (gpointer) icount);
+ }
+ g_mutex_unlock(&lock);
+
+ return &icount->count;
+ }
+ default:
+ g_assert_not_reached();
+ }
+
+ return NULL;
+}
+
+static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb)
+{
+ size_t n = qemu_plugin_tb_n_insns(tb);
+ size_t i;
+
+ for (i = 0; i < n; i++) {
+ uint64_t *cnt;
+ struct qemu_plugin_insn *insn = qemu_plugin_tb_get_insn(tb, i);
+ cnt = find_counter(insn);
+
+ if (cnt) {
+ if (do_inline) {
+ qemu_plugin_register_vcpu_insn_exec_inline(
+ insn, QEMU_PLUGIN_INLINE_ADD_U64, cnt, 1);
+ } else {
+ qemu_plugin_register_vcpu_insn_exec_cb(
+ insn, vcpu_insn_exec_before, QEMU_PLUGIN_CB_NO_REGS, cnt);
+ }
+ }
+ }
+}
+
+QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_id_t id,
+ const qemu_info_t *info,
+ int argc, char **argv)
+{
+ int i;
+
+ /* Select a class table appropriate to the guest architecture */
+ for (i = 0; i < ARRAY_SIZE(class_tables); i++) {
+ ClassSelector *entry = &class_tables[i];
+ if (!entry->qemu_target ||
+ strcmp(entry->qemu_target, info->target_name) == 0) {
+ class_table = entry->table;
+ class_table_sz = entry->table_sz;
+ break;
+ }
+ }
+
+ for (i = 0; i < argc; i++) {
+ char *p = argv[i];
+ if (strcmp(p, "inline") == 0) {
+ do_inline = true;
+ } else if (strcmp(p, "verbose") == 0) {
+ verbose = true;
+ } else {
+ int j;
+ CountType type = COUNT_INDIVIDUAL;
+ if (*p == '!') {
+ type = COUNT_NONE;
+ p++;
+ }
+ for (j = 0; j < class_table_sz; j++) {
+ if (strcmp(p, class_table[j].opt) == 0) {
+ class_table[j].what = type;
+ break;
+ }
+ }
+ }
+ }
+
+ plugin_init();
+
+ qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans);
+ qemu_plugin_register_atexit_cb(id, plugin_exit, NULL);
+ return 0;
+}
--
2.20.1
next prev parent reply other threads:[~2019-10-25 7:53 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-25 6:36 [PULL v2 00/73] tcg plugins and testing updates Alex Bennée
2019-10-25 6:36 ` [PULL v2 01/73] travis.yml: reduce scope of the --enable-debug build Alex Bennée
2019-10-25 6:36 ` [PULL v2 02/73] travis.yml: Add libvdeplug-dev to compile-test net/vde.c Alex Bennée
2019-10-25 6:36 ` [PULL v2 03/73] travis.yml: Use libsdl2 instead of libsdl1.2, and install libsdl2-image Alex Bennée
2019-10-25 6:36 ` [PULL v2 04/73] travis.yml: Use newer version of libgnutls and libpng Alex Bennée
2019-10-25 6:36 ` [PULL v2 05/73] travis.yml: Fix the ccache lines Alex Bennée
2019-10-25 6:36 ` [PULL v2 06/73] travis.yml: Test the release tarball Alex Bennée
2019-10-25 6:36 ` [PULL v2 07/73] travis.yml: bump Xcode 10 to latest dot release Alex Bennée
2019-10-25 6:36 ` [PULL v2 08/73] cirrus.yml: add latest Xcode build target Alex Bennée
2019-10-25 6:36 ` [PULL v2 09/73] tests/vm: netbsd autoinstall, using serial console Alex Bennée
2019-10-25 6:36 ` [PULL v2 10/73] tests/vm: Let subclasses disable IPv6 Alex Bennée
2019-10-25 6:36 ` [PULL v2 11/73] tests/vm/netbsd: Disable IPv6 Alex Bennée
2019-10-25 6:36 ` [PULL v2 12/73] travis.yml: cache the clang sanitizer build Alex Bennée
2019-10-25 6:36 ` [PULL v2 13/73] gitlab-ci.yml: Use libvdeplug-dev to compile-test the VDE network backend Alex Bennée
2019-10-25 6:36 ` [PULL v2 14/73] travis.yml: --enable-debug-tcg to check-tcg Alex Bennée
2019-10-25 6:36 ` [PULL v2 15/73] tests/docker: set HOST_ARCH if we don't have ARCH Alex Bennée
2019-10-25 6:36 ` [PULL v2 16/73] tests/docker: update Travis image to a more current version Alex Bennée
2019-10-25 6:36 ` [PULL v2 17/73] trace: expand mem_info:size_shift to 4 bits Alex Bennée
2019-10-25 6:36 ` [PULL v2 18/73] trace: add mmu_index to mem_info Alex Bennée
2019-10-25 6:36 ` [PULL v2 19/73] cpu: introduce cpu_in_exclusive_context() Alex Bennée
2019-10-25 6:36 ` [PULL v2 20/73] translate-all: use cpu_in_exclusive_work_context() in tb_flush Alex Bennée
2019-10-25 6:36 ` [PULL v2 21/73] docs/devel: add plugins.rst design document Alex Bennée
2019-10-25 6:36 ` [PULL v2 22/73] plugin: add user-facing API Alex Bennée
2019-10-25 6:36 ` [PULL v2 23/73] plugin: add core code Alex Bennée
2019-10-25 6:36 ` [PULL v2 24/73] plugin: add implementation of the api Alex Bennée
2019-10-25 6:36 ` [PULL v2 25/73] queue: add QTAILQ_REMOVE_SEVERAL Alex Bennée
2019-10-25 6:36 ` [PULL v2 26/73] cputlb: document get_page_addr_code Alex Bennée
2019-10-25 6:36 ` [PULL v2 27/73] cputlb: introduce get_page_addr_code_hostp Alex Bennée
2019-10-25 6:36 ` [PULL v2 28/73] tcg: add tcg_gen_st_ptr Alex Bennée
2019-10-25 6:36 ` [PULL v2 29/73] plugin-gen: add module for TCG-related code Alex Bennée
2019-10-25 6:36 ` [PULL v2 30/73] atomic_template: add inline trace/plugin helpers Alex Bennée
2019-10-25 6:36 ` [PULL v2 31/73] tcg: let plugins instrument virtual memory accesses Alex Bennée
2019-10-25 6:36 ` [PULL v2 32/73] plugins: implement helpers for resolving hwaddr Alex Bennée
2019-10-25 6:36 ` [PULL v2 33/73] translate-all: notify plugin code of tb_flush Alex Bennée
2019-10-25 6:36 ` [PULL v2 34/73] *-user: notify plugin of exit Alex Bennée
2019-10-25 6:36 ` [PULL v2 35/73] *-user: plugin syscalls Alex Bennée
2019-10-25 6:36 ` [PULL v2 36/73] cpu: hook plugin vcpu events Alex Bennée
2019-10-25 6:36 ` [PULL v2 37/73] plugin-gen: add plugin_insn_append Alex Bennée
2019-10-25 6:36 ` [PULL v2 38/73] cputlb: ensure _cmmu helper functions follow the naming standard Alex Bennée
2019-10-25 6:36 ` [PULL v2 39/73] translator: add translator_ld{ub,sw,uw,l,q} Alex Bennée
2019-10-25 6:36 ` [PULL v2 40/73] target/arm: fetch code with translator_ld Alex Bennée
2019-10-25 6:36 ` [PULL v2 41/73] target/ppc: " Alex Bennée
2019-10-25 6:36 ` [PULL v2 42/73] target/sh4: " Alex Bennée
2019-10-25 6:36 ` [PULL v2 43/73] target/i386: " Alex Bennée
2019-10-25 6:36 ` [PULL v2 44/73] target/hppa: " Alex Bennée
2019-10-25 6:36 ` [PULL v2 45/73] target/m68k: " Alex Bennée
2019-10-25 6:36 ` [PULL v2 46/73] target/alpha: " Alex Bennée
2019-10-25 7:40 ` USB-audio sound issues with qemu-system-ppc in Linux and Windows Howard Spoelstra
2019-10-25 6:36 ` [PULL v2 47/73] target/riscv: fetch code with translator_ld Alex Bennée
2019-10-25 6:36 ` [PULL v2 48/73] target/sparc: " Alex Bennée
2019-10-25 6:36 ` [PULL v2 49/73] target/xtensa: " Alex Bennée
2019-10-25 6:36 ` [PULL v2 50/73] target/openrisc: " Alex Bennée
2019-10-25 6:36 ` [PULL v2 51/73] translator: inject instrumentation from plugins Alex Bennée
2019-10-25 6:36 ` [PULL v2 52/73] configure: add --enable-plugins Alex Bennée
2019-10-25 6:36 ` [PULL v2 53/73] plugin: add API symbols to qemu-plugins.symbols Alex Bennée
2019-10-25 6:36 ` [PULL v2 54/73] plugin: expand the plugin_init function to include an info block Alex Bennée
2019-10-25 6:36 ` [PULL v2 55/73] plugin: add qemu_plugin_insn_disas helper Alex Bennée
2019-10-25 6:36 ` [PULL v2 56/73] plugin: add qemu_plugin_outs helper Alex Bennée
2019-10-25 6:36 ` [PULL v2 57/73] vl: support -plugin option Alex Bennée
2019-10-25 6:36 ` [PULL v2 58/73] linux-user: " Alex Bennée
2019-10-25 6:36 ` [PULL v2 59/73] tests/plugin: add sample plugins Alex Bennée
2019-10-25 6:37 ` [PULL v2 60/73] tests/tcg/Makefile.target: fix path to config-host.mak Alex Bennée
2019-10-25 6:37 ` [PULL v2 61/73] tests/tcg: set QEMU_OPTS for all cris runs Alex Bennée
2019-10-25 6:37 ` [PULL v2 62/73] tests/tcg: move "virtual" tests to EXTRA_TESTS Alex Bennée
2019-10-25 6:37 ` [PULL v2 63/73] tests/tcg: drop test-i386-fprem from TESTS when not SLOW Alex Bennée
2019-10-25 6:37 ` [PULL v2 64/73] tests/tcg: enable plugin testing Alex Bennée
2019-10-25 6:37 ` [PULL v2 65/73] tests/plugin: add a hotblocks plugin Alex Bennée
2019-10-25 6:37 ` Alex Bennée [this message]
2019-10-25 6:37 ` [PULL v2 67/73] tests/plugin: add hotpages to analyse memory access patterns Alex Bennée
2019-10-25 6:37 ` [PULL v2 68/73] accel/stubs: reduce headers from tcg-stub Alex Bennée
2019-10-25 6:37 ` [PULL v2 69/73] include/exec: wrap cpu_ldst.h in CONFIG_TCG Alex Bennée
2019-10-25 6:37 ` [PULL v2 70/73] .travis.yml: add --enable-plugins tests Alex Bennée
2019-10-25 6:37 ` [PULL v2 71/73] scripts/checkpatch.pl: don't complain about (foo, /* empty */) Alex Bennée
2019-10-25 6:37 ` [PULL v2 72/73] MAINTAINERS: add me for the TCG plugins code Alex Bennée
2019-10-25 6:37 ` [PULL v2 73/73] travis.yml: enable linux-gcc-debug-tcg cache Alex Bennée
2019-10-25 12:59 ` [PULL v2 00/73] tcg plugins and testing updates Markus Armbruster
2019-10-25 15:04 ` Alex Bennée
2019-10-25 20:23 ` Markus Armbruster
2019-10-27 19:44 ` Peter Maydell
2019-10-28 9:07 ` Alex Bennée
2019-11-06 12:42 ` Markus Armbruster
2019-11-08 17:23 ` Peter Maydell
2019-10-25 16:53 ` Peter Maydell
2019-10-25 19:38 ` Alex Bennée
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