From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, alex.bennee@linaro.org
Subject: [PATCH v4 05/20] target/arm: Split out aarch32_cpsr_valid_mask
Date: Sat, 8 Feb 2020 12:58:01 +0000 [thread overview]
Message-ID: <20200208125816.14954-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org>
Split this helper out of msr_mask in translate.c. At the same time,
transform the negative reductive logic to positive accumulative logic.
It will be usable along the exception paths.
While touching msr_mask, fix up formatting.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v4: Keep CPSR_J unconditionally in this patch.
Fix all formatting in msr_mask.
---
target/arm/internals.h | 21 +++++++++++++++++++++
target/arm/translate.c | 40 +++++++++++++++++-----------------------
2 files changed, 38 insertions(+), 23 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 6be8b2d1a9..4d4896fcdc 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1061,6 +1061,27 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx)
}
}
+static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
+ const ARMISARegisters *id)
+{
+ uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV | CPSR_J;
+
+ if ((features >> ARM_FEATURE_V4T) & 1) {
+ valid |= CPSR_T;
+ }
+ if ((features >> ARM_FEATURE_V5) & 1) {
+ valid |= CPSR_Q; /* V5TE in reality*/
+ }
+ if ((features >> ARM_FEATURE_V6) & 1) {
+ valid |= CPSR_E | CPSR_GE;
+ }
+ if ((features >> ARM_FEATURE_THUMB2) & 1) {
+ valid |= CPSR_IT;
+ }
+
+ return valid;
+}
+
/*
* Parameters of a given virtual address, as extracted from the
* translation control register (TCR) for a given regime.
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d58c328e08..20f89ace2f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -2734,39 +2734,33 @@ static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y)
/* Return the mask of PSR bits set by a MSR instruction. */
static uint32_t msr_mask(DisasContext *s, int flags, int spsr)
{
- uint32_t mask;
+ uint32_t mask = 0;
- mask = 0;
- if (flags & (1 << 0))
+ if (flags & (1 << 0)) {
mask |= 0xff;
- if (flags & (1 << 1))
+ }
+ if (flags & (1 << 1)) {
mask |= 0xff00;
- if (flags & (1 << 2))
+ }
+ if (flags & (1 << 2)) {
mask |= 0xff0000;
- if (flags & (1 << 3))
+ }
+ if (flags & (1 << 3)) {
mask |= 0xff000000;
+ }
- /* Mask out undefined bits. */
- mask &= ~CPSR_RESERVED;
- if (!arm_dc_feature(s, ARM_FEATURE_V4T)) {
- mask &= ~CPSR_T;
- }
- if (!arm_dc_feature(s, ARM_FEATURE_V5)) {
- mask &= ~CPSR_Q; /* V5TE in reality*/
- }
- if (!arm_dc_feature(s, ARM_FEATURE_V6)) {
- mask &= ~(CPSR_E | CPSR_GE);
- }
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
- mask &= ~CPSR_IT;
- }
- /* Mask out execution state and reserved bits. */
+ /* Mask out undefined and reserved bits. */
+ mask &= aarch32_cpsr_valid_mask(s->features, s->isar);
+
+ /* Mask out execution state. */
if (!spsr) {
- mask &= ~(CPSR_EXEC | CPSR_RESERVED);
+ mask &= ~CPSR_EXEC;
}
+
/* Mask out privileged bits. */
- if (IS_USER(s))
+ if (IS_USER(s)) {
mask &= CPSR_USER;
+ }
return mask;
}
--
2.20.1
next prev parent reply other threads:[~2020-02-08 13:01 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-08 12:57 [PATCH v4 00/20] target/arm: Implement PAN, ATS1E1, UAO Richard Henderson
2020-02-08 12:57 ` [PATCH v4 01/20] target/arm: Add arm_mmu_idx_is_stage1_of_2 Richard Henderson
2020-02-08 12:57 ` [PATCH v4 02/20] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled Richard Henderson
2020-02-08 12:57 ` [PATCH v4 03/20] target/arm: Add isar_feature tests for PAN + ATS1E1 Richard Henderson
2020-02-14 11:28 ` Peter Maydell
2020-02-14 16:20 ` Peter Maydell
2020-02-14 18:19 ` Richard Henderson
2020-02-08 12:58 ` [PATCH v4 04/20] target/arm: Move LOR regdefs to file scope Richard Henderson
2020-02-08 12:58 ` Richard Henderson [this message]
2020-02-11 18:06 ` [PATCH v4 05/20] target/arm: Split out aarch32_cpsr_valid_mask Peter Maydell
2020-02-08 12:58 ` [PATCH v4 06/20] target/arm: Mask CPSR_J when Jazelle is not enabled Richard Henderson
2020-02-11 18:07 ` Peter Maydell
2020-02-08 12:58 ` [PATCH v4 07/20] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask Richard Henderson
2020-02-08 12:58 ` [PATCH v4 08/20] target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return Richard Henderson
2020-02-08 12:58 ` [PATCH v4 09/20] target/arm: Remove CPSR_RESERVED Richard Henderson
2020-02-11 18:07 ` Peter Maydell
2020-02-08 12:58 ` [PATCH v4 10/20] target/arm: Introduce aarch64_pstate_valid_mask Richard Henderson
2020-02-08 12:58 ` [PATCH v4 11/20] target/arm: Update MSR access for PAN Richard Henderson
2020-02-08 12:58 ` [PATCH v4 12/20] target/arm: Update arm_mmu_idx_el " Richard Henderson
2020-02-08 12:58 ` [PATCH v4 13/20] target/arm: Enforce PAN semantics in get_S1prot Richard Henderson
2020-02-08 12:58 ` [PATCH v4 14/20] target/arm: Set PAN bit as required on exception entry Richard Henderson
2020-02-11 18:09 ` Peter Maydell
2020-02-08 12:58 ` [PATCH v4 15/20] target/arm: Implement ATS1E1 system registers Richard Henderson
2020-02-08 12:58 ` [PATCH v4 16/20] target/arm: Enable ARMv8.2-ATS1E1 in -cpu max Richard Henderson
2020-02-08 12:58 ` [PATCH v4 17/20] target/arm: Add ID_AA64MMFR2_EL1 Richard Henderson
2020-02-08 12:58 ` [PATCH v4 18/20] target/arm: Update MSR access to UAO Richard Henderson
2020-02-08 12:58 ` [PATCH v4 19/20] target/arm: Implement UAO semantics Richard Henderson
2020-02-08 12:58 ` [PATCH v4 20/20] target/arm: Enable ARMv8.2-UAO in -cpu max Richard Henderson
2020-02-11 18:41 ` [PATCH v4 00/20] target/arm: Implement PAN, ATS1E1, UAO Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200208125816.14954-6-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=alex.bennee@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).