Re: [PATCH v2 3/3] uninorth: use qdev gpios for PCI IRQs

[David Gibson <david@gibson.dropbear.id.au>]

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On Tue, Oct 13, 2020 at 05:58:52PM +0100, Mark Cave-Ayland wrote:
> On 13/10/2020 14:38, BALATON Zoltan via wrote:
> 
> > On Tue, 13 Oct 2020, Mark Cave-Ayland wrote:
> > > Currently an object link property is used to pass a reference to the OpenPIC
> > > into the PCI host bridge so that pci_unin_init_irqs() can connect the PCI
> > > IRQs to the PIC itself.
> > > 
> > > This can be simplified by defining the PCI IRQs as qdev gpios and then wiring
> > > up the PCI IRQs to the PIC in the New World machine init function.
> > > 
> > > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> > > ---
> > > hw/pci-host/uninorth.c         | 45 +++++++---------------------------
> > > hw/ppc/mac_newworld.c          | 24 ++++++++++++------
> > > include/hw/pci-host/uninorth.h |  2 --
> > > 3 files changed, 25 insertions(+), 46 deletions(-)
> > > 
> > > diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
> > > index 1ed1072eeb..0c0a9ecee1 100644
> > > --- a/hw/pci-host/uninorth.c
> > > +++ b/hw/pci-host/uninorth.c
> > > @@ -32,8 +32,6 @@
> > > #include "hw/pci-host/uninorth.h"
> > > #include "trace.h"
> > > 
> > > -static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
> > > -
> > > static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
> > > {
> > >     return (irq_num + (pci_dev->devfn >> 3)) & 3;
> > > @@ -43,7 +41,7 @@ static void pci_unin_set_irq(void *opaque, int irq_num, int level)
> > > {
> > >     UNINHostState *s = opaque;
> > > 
> > > -    trace_unin_set_irq(unin_irq_line[irq_num], level);
> > > +    trace_unin_set_irq(irq_num, level);
> > >     qemu_set_irq(s->irqs[irq_num], level);
> > > }
> > > 
> > > @@ -112,15 +110,6 @@ static const MemoryRegionOps unin_data_ops = {
> > >     .endianness = DEVICE_LITTLE_ENDIAN,
> > > };
> > > 
> > > -static void pci_unin_init_irqs(UNINHostState *s)
> > > -{
> > > -    int i;
> > > -
> > > -    for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
> > > -        s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), unin_irq_line[i]);
> > > -    }
> > > -}
> > > -
> > > static char *pci_unin_main_ofw_unit_address(const SysBusDevice *dev)
> > > {
> > >     UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
> > > @@ -141,7 +130,6 @@ static void pci_unin_main_realize(DeviceState *dev, Error **errp)
> > >                                    PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
> > > 
> > >     pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci");
> > > -    pci_unin_init_irqs(s);
> > > 
> > >     /* DEC 21154 bridge */
> > > #if 0
> > > @@ -172,15 +160,12 @@ static void pci_unin_main_init(Object *obj)
> > >                              "unin-pci-hole", &s->pci_mmio,
> > >                              0x80000000ULL, 0x10000000ULL);
> > > 
> > > -    object_property_add_link(obj, "pic", TYPE_OPENPIC,
> > > -                             (Object **) &s->pic,
> > > -                             qdev_prop_allow_set_link_before_realize,
> > > -                             0);
> > > -
> > >     sysbus_init_mmio(sbd, &h->conf_mem);
> > >     sysbus_init_mmio(sbd, &h->data_mem);
> > >     sysbus_init_mmio(sbd, &s->pci_hole);
> > >     sysbus_init_mmio(sbd, &s->pci_io);
> > > +
> > > +    qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
> > > }
> > > 
> > > static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
> > > @@ -196,7 +181,6 @@ static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
> > >                                    PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
> > > 
> > >     pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp");
> > > -    pci_unin_init_irqs(s);
> > > }
> > > 
> > > static void pci_u3_agp_init(Object *obj)
> > > @@ -220,15 +204,12 @@ static void pci_u3_agp_init(Object *obj)
> > >                              "unin-pci-hole", &s->pci_mmio,
> > >                              0x80000000ULL, 0x70000000ULL);
> > > 
> > > -    object_property_add_link(obj, "pic", TYPE_OPENPIC,
> > > -                             (Object **) &s->pic,
> > > -                             qdev_prop_allow_set_link_before_realize,
> > > -                             0);
> > > -
> > >     sysbus_init_mmio(sbd, &h->conf_mem);
> > >     sysbus_init_mmio(sbd, &h->data_mem);
> > >     sysbus_init_mmio(sbd, &s->pci_hole);
> > >     sysbus_init_mmio(sbd, &s->pci_io);
> > > +
> > > +    qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
> > > }
> > > 
> > > static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
> > > @@ -244,7 +225,6 @@ static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
> > >                                    PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
> > > 
> > >     pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
> > > -    pci_unin_init_irqs(s);
> > > }
> > > 
> > > static void pci_unin_agp_init(Object *obj)
> > > @@ -259,13 +239,10 @@ static void pci_unin_agp_init(Object *obj)
> > >     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
> > >                           obj, "unin-agp-conf-data", 0x1000);
> > > 
> > > -    object_property_add_link(obj, "pic", TYPE_OPENPIC,
> > > -                             (Object **) &s->pic,
> > > -                             qdev_prop_allow_set_link_before_realize,
> > > -                             0);
> > > -
> > >     sysbus_init_mmio(sbd, &h->conf_mem);
> > >     sysbus_init_mmio(sbd, &h->data_mem);
> > > +
> > > +    qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
> > > }
> > > 
> > > static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
> > > @@ -281,7 +258,6 @@ static void
> > > pci_unin_internal_realize(DeviceState *dev, Error **errp)
> > >                                    PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS);
> > > 
> > >     pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci");
> > > -    pci_unin_init_irqs(s);
> > > }
> > > 
> > > static void pci_unin_internal_init(Object *obj)
> > > @@ -296,13 +272,10 @@ static void pci_unin_internal_init(Object *obj)
> > >     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
> > >                           obj, "unin-pci-conf-data", 0x1000);
> > > 
> > > -    object_property_add_link(obj, "pic", TYPE_OPENPIC,
> > > -                             (Object **) &s->pic,
> > > -                             qdev_prop_allow_set_link_before_realize,
> > > -                             0);
> > > -
> > >     sysbus_init_mmio(sbd, &h->conf_mem);
> > >     sysbus_init_mmio(sbd, &h->data_mem);
> > > +
> > > +    qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
> > > }
> > > 
> > > static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
> > > diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
> > > index 6f5ef2e782..7a8dc09c8d 100644
> > > --- a/hw/ppc/mac_newworld.c
> > > +++ b/hw/ppc/mac_newworld.c
> > > @@ -303,8 +303,6 @@ static void ppc_core99_init(MachineState *machine)
> > >         /* 970 gets a U3 bus */
> > >         /* Uninorth AGP bus */
> > >         dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE);
> > > -        object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev),
> > > -                                 &error_abort);
> > >         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> > >         uninorth_pci = U3_AGP_HOST_BRIDGE(dev);
> > >         s = SYS_BUS_DEVICE(dev);
> > > @@ -317,32 +315,38 @@ static void ppc_core99_init(MachineState *machine)
> > >         sysbus_mmio_map(s, 0, 0xf0800000);
> > >         sysbus_mmio_map(s, 1, 0xf0c00000);
> > > 
> > > +        for (i = 0; i < 4; i++) {
> > 
> > Philippe had a series that replaced all these with PCI_NUM_IRQS or
> > similar constant. Should you use that instead in new additions?
> 
> I'm not sure that's directly relevant here - my understanding was that
> PCI_NUM_IRQS represents the number of IRQs on the device, not the PCI host
> bridge. Certainly it could be argued that there is a 1:1 correspondence in
> this case, however I don't have any documentation to support this so it
> doesn't feel right to make these values directly equivalent.

I think it's the same thing.  On legacy PCI there are 4 interrupt
lines (INTA..INTD).  Each device can use any or all of those (though
they usually only use one per function in practice).  Bridges swizzle
which pins on the downstream bus are wired to which pins on the
upstream bus, but there's still just 4 of them all the way up to the
host bridge, which will then wire those 4 up to system PIC lines one
way or another.

On-board devices often have (had?) a sideband interrupt wired directly
to the PIC, rather than using one of the bus lines.

> > This is probably not modelled faithfuly (the whole mac99 machine is a
> > hack to get the most OSes run, not emulating an actual machine) but I
> > wonder if it's correct to connect all these irqs for all the different
> > busses to the same pic lines? Is that how it is on a real PowerMac3,1?
> > (This is just a question not something that should be fixed in this
> > patch which is a nice clean up anyway, this just made it more obvious to
> > me what's happening so maybe we can find out a difference in emulation
> > compared to real hardware that could be fixed in the future.)
> 
> Yeah I spotted that too when I was writing the patch. In its current form it
> keeps the existing behaviour as-is, but this is something that may be worth
> investigating later. I'm not aware of any documentation explaining how the
> PCI/AGP bridges are wired up on a Mac, so it might end up being a case of
> trawling through driver source code to try and get some answers...

It's worth checking, but having them all wired together isn't that
implausible.  In that pre-MSI era some weird wirings and heavily
shared irq lines are pretty common.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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