From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 06/11] target/arm: Enforce alignment for VLDM/VSTM
Date: Tue, 24 Nov 2020 20:06:37 -0800 [thread overview]
Message-ID: <20201125040642.2339476-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20201125040642.2339476-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-vfp.c.inc | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index 96948f5a2d..58b31ecc3f 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -1065,12 +1065,14 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
for (i = 0; i < n; i++) {
if (a->l) {
/* load */
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
+ MO_UL | MO_ALIGN | s->be_data);
vfp_store_reg32(tmp, a->vd + i);
} else {
/* store */
vfp_load_reg32(tmp, a->vd + i);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
+ MO_UL | MO_ALIGN | s->be_data);
}
tcg_gen_addi_i32(addr, addr, offset);
}
@@ -1148,12 +1150,14 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
for (i = 0; i < n; i++) {
if (a->l) {
/* load */
- gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s),
+ MO_Q | MO_ALIGN_4 | s->be_data);
vfp_store_reg64(tmp, a->vd + i);
} else {
/* store */
vfp_load_reg64(tmp, a->vd + i);
- gen_aa32_st64(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i64(s, tmp, addr, get_mem_index(s),
+ MO_Q | MO_ALIGN_4 | s->be_data);
}
tcg_gen_addi_i32(addr, addr, offset);
}
--
2.25.1
next prev parent reply other threads:[~2020-11-25 4:10 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-25 4:06 [PATCH for-6.0 00/11] target/arm: enforce alignment Richard Henderson
2020-11-25 4:06 ` [PATCH 01/11] target/arm: Enforce word alignment for LDRD/STRD Richard Henderson
2020-11-25 8:11 ` Philippe Mathieu-Daudé
2020-11-25 4:06 ` [PATCH 02/11] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
2020-11-25 8:13 ` Philippe Mathieu-Daudé
2020-11-25 4:06 ` [PATCH 03/11] target/arm: Enforce alignment for LDM/STM Richard Henderson
2020-11-25 4:06 ` [PATCH 04/11] target/arm: Enforce alignment for RFE Richard Henderson
2020-11-25 4:06 ` [PATCH 05/11] target/arm: Enforce alignment for SRS Richard Henderson
2020-12-03 11:38 ` Peter Maydell
2020-11-25 4:06 ` Richard Henderson [this message]
2020-11-25 4:06 ` [PATCH 07/11] target/arm: Enforce alignment for VLDR/VSTR Richard Henderson
2020-11-25 4:06 ` [PATCH 08/11] target/arm: Enforce alignment for VLD1 (all lanes) Richard Henderson
2020-11-25 4:06 ` [PATCH 09/11] target/arm: Enforce alignment for VLDn/VSTn (multiple) Richard Henderson
2020-11-25 4:06 ` [PATCH 10/11] target/arm: Fix decode of align in VLDST_single Richard Henderson
2020-12-01 14:09 ` Peter Maydell
2020-11-25 4:06 ` [PATCH 11/11] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
2020-12-01 14:27 ` [PATCH for-6.0 00/11] target/arm: enforce alignment Peter Maydell
2020-12-01 14:37 ` Richard Henderson
2020-12-01 15:55 ` Peter Maydell
2020-12-03 12:30 ` Philippe Mathieu-Daudé
2020-12-03 16:10 ` Pavel Dovgalyuk
2020-12-03 16:14 ` Peter Maydell
2020-12-04 6:17 ` Pavel Dovgalyuk
2020-12-04 16:36 ` Peter Maydell
2020-12-04 17:28 ` Richard Henderson
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