From: Claudio Fontana <cfontana@suse.de>
To: "Alex Bennée" <alex.bennee@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Eduardo Habkost" <ehabkost@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>
Cc: Laurent Vivier <lvivier@redhat.com>,
Thomas Huth <thuth@redhat.com>,
Roman Bolshakov <r.bolshakov@yadro.com>,
Claudio Fontana <cfontana@suse.de>,
qemu-devel@nongnu.org
Subject: [RFC v18 12/15] i386: separate fpu_helper into user and softmmu parts
Date: Fri, 12 Feb 2021 13:36:19 +0100 [thread overview]
Message-ID: <20210212123622.15834-13-cfontana@suse.de> (raw)
In-Reply-To: <20210212123622.15834-1-cfontana@suse.de>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/i386/cpu.h | 3 ++
target/i386/tcg/fpu_helper.c | 65 +---------------------------
target/i386/tcg/softmmu/fpu_helper.c | 58 +++++++++++++++++++++++++
target/i386/tcg/user/fpu_helper.c | 42 ++++++++++++++++++
target/i386/tcg/softmmu/meson.build | 1 +
target/i386/tcg/user/meson.build | 1 +
6 files changed, 107 insertions(+), 63 deletions(-)
create mode 100644 target/i386/tcg/softmmu/fpu_helper.c
create mode 100644 target/i386/tcg/user/fpu_helper.c
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index a4f9bbef55..afcf34e40b 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1811,7 +1811,10 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env);
int cpu_get_pic_interrupt(CPUX86State *s);
/* MSDOS compatibility mode FPU exception support */
void x86_register_ferr_irq(qemu_irq irq);
+bool fpu_check_raise_ferr_irq(CPUX86State *s);
void cpu_set_ignne(void);
+void cpu_clear_ignne(void);
+
/* mpx_helper.c */
void cpu_sync_bndcs_hflags(CPUX86State *env);
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 60ed93520a..257d121746 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -21,17 +21,10 @@
#include <math.h>
#include "cpu.h"
#include "exec/helper-proto.h"
-#include "qemu/host-utils.h"
-#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
#include "fpu/softfloat.h"
#include "fpu/softfloat-macros.h"
#include "helper-tcg.h"
-#ifdef CONFIG_SOFTMMU
-#include "hw/irq.h"
-#endif
-
/* float macros */
#define FT0 (env->ft0)
#define ST0 (env->fpregs[env->fpstt].d)
@@ -75,36 +68,6 @@
#define floatx80_ln2_d make_floatx80(0x3ffe, 0xb17217f7d1cf79abLL)
#define floatx80_pi_d make_floatx80(0x4000, 0xc90fdaa22168c234LL)
-#if !defined(CONFIG_USER_ONLY)
-static qemu_irq ferr_irq;
-
-void x86_register_ferr_irq(qemu_irq irq)
-{
- ferr_irq = irq;
-}
-
-static void cpu_clear_ignne(void)
-{
- CPUX86State *env = &X86_CPU(first_cpu)->env;
- env->hflags2 &= ~HF2_IGNNE_MASK;
-}
-
-void cpu_set_ignne(void)
-{
- CPUX86State *env = &X86_CPU(first_cpu)->env;
- env->hflags2 |= HF2_IGNNE_MASK;
- /*
- * We get here in response to a write to port F0h. The chipset should
- * deassert FP_IRQ and FERR# instead should stay signaled until FPSW_SE is
- * cleared, because FERR# and FP_IRQ are two separate pins on real
- * hardware. However, we don't model FERR# as a qemu_irq, so we just
- * do directly what the chipset would do, i.e. deassert FP_IRQ.
- */
- qemu_irq_lower(ferr_irq);
-}
-#endif
-
-
static inline void fpush(CPUX86State *env)
{
env->fpstt = (env->fpstt - 1) & 7;
@@ -203,8 +166,8 @@ static void fpu_raise_exception(CPUX86State *env, uintptr_t retaddr)
raise_exception_ra(env, EXCP10_COPR, retaddr);
}
#if !defined(CONFIG_USER_ONLY)
- else if (ferr_irq && !(env->hflags2 & HF2_IGNNE_MASK)) {
- qemu_irq_raise(ferr_irq);
+ else {
+ (void)fpu_check_raise_ferr_irq(env);
}
#endif
}
@@ -2501,18 +2464,6 @@ void helper_frstor(CPUX86State *env, target_ulong ptr, int data32)
}
}
-#if defined(CONFIG_USER_ONLY)
-void cpu_x86_fsave(CPUX86State *env, target_ulong ptr, int data32)
-{
- helper_fsave(env, ptr, data32);
-}
-
-void cpu_x86_frstor(CPUX86State *env, target_ulong ptr, int data32)
-{
- helper_frstor(env, ptr, data32);
-}
-#endif
-
#define XO(X) offsetof(X86XSaveArea, X)
static void do_xsave_fpu(CPUX86State *env, target_ulong ptr, uintptr_t ra)
@@ -2780,18 +2731,6 @@ void helper_fxrstor(CPUX86State *env, target_ulong ptr)
}
}
-#if defined(CONFIG_USER_ONLY)
-void cpu_x86_fxsave(CPUX86State *env, target_ulong ptr)
-{
- helper_fxsave(env, ptr);
-}
-
-void cpu_x86_fxrstor(CPUX86State *env, target_ulong ptr)
-{
- helper_fxrstor(env, ptr);
-}
-#endif
-
void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
{
uintptr_t ra = GETPC();
diff --git a/target/i386/tcg/softmmu/fpu_helper.c b/target/i386/tcg/softmmu/fpu_helper.c
new file mode 100644
index 0000000000..eea9304973
--- /dev/null
+++ b/target/i386/tcg/softmmu/fpu_helper.c
@@ -0,0 +1,58 @@
+/*
+ * x86 FPU, MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI helpers (softmmu code)
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "hw/irq.h"
+
+static qemu_irq ferr_irq;
+
+void x86_register_ferr_irq(qemu_irq irq)
+{
+ ferr_irq = irq;
+}
+
+bool fpu_check_raise_ferr_irq(CPUX86State *env)
+{
+ if (ferr_irq && !(env->hflags2 & HF2_IGNNE_MASK)) {
+ qemu_irq_raise(ferr_irq);
+ return true;
+ }
+ return false;
+}
+
+void cpu_clear_ignne(void)
+{
+ CPUX86State *env = &X86_CPU(first_cpu)->env;
+ env->hflags2 &= ~HF2_IGNNE_MASK;
+}
+
+void cpu_set_ignne(void)
+{
+ CPUX86State *env = &X86_CPU(first_cpu)->env;
+ env->hflags2 |= HF2_IGNNE_MASK;
+ /*
+ * We get here in response to a write to port F0h. The chipset should
+ * deassert FP_IRQ and FERR# instead should stay signaled until FPSW_SE is
+ * cleared, because FERR# and FP_IRQ are two separate pins on real
+ * hardware. However, we don't model FERR# as a qemu_irq, so we just
+ * do directly what the chipset would do, i.e. deassert FP_IRQ.
+ */
+ qemu_irq_lower(ferr_irq);
+}
diff --git a/target/i386/tcg/user/fpu_helper.c b/target/i386/tcg/user/fpu_helper.c
new file mode 100644
index 0000000000..bb6f21fed8
--- /dev/null
+++ b/target/i386/tcg/user/fpu_helper.c
@@ -0,0 +1,42 @@
+/*
+ * x86 FPU, MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI helpers (user-mode)
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+
+void cpu_x86_fsave(CPUX86State *env, target_ulong ptr, int data32)
+{
+ helper_fsave(env, ptr, data32);
+}
+
+void cpu_x86_frstor(CPUX86State *env, target_ulong ptr, int data32)
+{
+ helper_frstor(env, ptr, data32);
+}
+
+void cpu_x86_fxsave(CPUX86State *env, target_ulong ptr)
+{
+ helper_fxsave(env, ptr);
+}
+
+void cpu_x86_fxrstor(CPUX86State *env, target_ulong ptr)
+{
+ helper_fxrstor(env, ptr);
+}
diff --git a/target/i386/tcg/softmmu/meson.build b/target/i386/tcg/softmmu/meson.build
index b2aaab6eef..f84519a213 100644
--- a/target/i386/tcg/softmmu/meson.build
+++ b/target/i386/tcg/softmmu/meson.build
@@ -4,4 +4,5 @@ i386_softmmu_ss.add(when: ['CONFIG_TCG', 'CONFIG_SOFTMMU'], if_true: files(
'excp_helper.c',
'bpt_helper.c',
'misc_helper.c',
+ 'fpu_helper.c',
))
diff --git a/target/i386/tcg/user/meson.build b/target/i386/tcg/user/meson.build
index fb8cdc13ef..30eec3f5a4 100644
--- a/target/i386/tcg/user/meson.build
+++ b/target/i386/tcg/user/meson.build
@@ -1,4 +1,5 @@
i386_user_ss.add(when: ['CONFIG_TCG', 'CONFIG_USER_ONLY'], if_true: files(
'excp_helper.c',
'misc_helper.c',
+ 'fpu_helper.c',
))
--
2.26.2
next prev parent reply other threads:[~2021-02-12 12:44 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 12:36 [RFC v18 00/15] i386 cleanup PART 2 Claudio Fontana
2021-02-12 12:36 ` [RFC v18 01/15] i386: split cpu accelerators from cpu.c, using AccelCPUClass Claudio Fontana
2021-02-15 11:29 ` Alex Bennée
2021-02-12 12:36 ` [RFC v18 02/15] cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefn Claudio Fontana
2021-02-15 11:30 ` Alex Bennée
2021-02-12 12:36 ` [RFC v18 03/15] accel: introduce new accessor functions Claudio Fontana
2021-02-15 11:34 ` Alex Bennée
2021-02-12 12:36 ` [RFC v18 04/15] target/i386: fix host_cpu_adjust_phys_bits error handling Claudio Fontana
2021-02-12 12:36 ` [RFC v18 05/15] accel-cpu: make cpu_realizefn return a bool Claudio Fontana
2021-02-12 12:36 ` [RFC v18 06/15] meson: add target_user_arch Claudio Fontana
2021-02-15 11:37 ` Alex Bennée
2021-02-12 12:36 ` [RFC v18 07/15] i386: split off softmmu-only functionality in tcg-cpu Claudio Fontana
2021-02-12 12:36 ` [RFC v18 08/15] i386: split smm helper (softmmu) Claudio Fontana
2021-02-15 11:51 ` Claudio Fontana
2021-02-15 12:32 ` Alex Bennée
2021-02-15 12:59 ` Claudio Fontana
2021-02-15 13:30 ` Paolo Bonzini
2021-02-15 14:05 ` Claudio Fontana
2021-02-15 14:13 ` Paolo Bonzini
2021-02-15 14:39 ` Claudio Fontana
2021-02-15 15:33 ` Claudio Fontana
2021-02-12 12:36 ` [RFC v18 09/15] i386: split tcg excp_helper into softmmu and user parts Claudio Fontana
2021-02-12 12:36 ` [RFC v18 10/15] i386: split tcg btp_helper " Claudio Fontana
2021-02-15 11:55 ` Claudio Fontana
2021-02-12 12:36 ` [RFC v18 11/15] i386: split misc helper into user and softmmu parts Claudio Fontana
2021-02-12 12:36 ` Claudio Fontana [this message]
2021-02-15 10:32 ` [RFC v18 12/15] i386: separate fpu_helper " Alex Bennée
2021-02-12 12:36 ` [RFC v18 13/15] i386: slit svm_helper into softmmu and stub-only user Claudio Fontana
2021-02-12 12:36 ` [RFC v18 14/15] i386: split seg_helper into user-only and softmmu parts Claudio Fontana
2021-02-12 12:36 ` [RFC v18 15/15] i386: split off softmmu part of cpu.c Claudio Fontana
2021-02-12 12:57 ` [RFC v18 00/15] i386 cleanup PART 2 no-reply
2021-02-15 11:37 ` Alex Bennée
2021-02-15 11:48 ` Claudio Fontana
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210212123622.15834-13-cfontana@suse.de \
--to=cfontana@suse.de \
--cc=alex.bennee@linaro.org \
--cc=ehabkost@redhat.com \
--cc=lvivier@redhat.com \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=philmd@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=r.bolshakov@yadro.com \
--cc=richard.henderson@linaro.org \
--cc=thuth@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).