From: Claudio Fontana <cfontana@suse.de>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Roman Bolshakov <r.bolshakov@yadro.com>,
Claudio Fontana <cfontana@suse.de>,
Eduardo Habkost <ehabkost@redhat.com>,
qemu-devel@nongnu.org
Subject: [RFC v3 16/23] target/arm: move sve_zcr_len_for_el to common_cpu
Date: Wed, 3 Mar 2021 12:40:46 +0100 [thread overview]
Message-ID: <20210303114053.20305-17-cfontana@suse.de> (raw)
In-Reply-To: <20210303114053.20305-1-cfontana@suse.de>
it is required by arch-dump.c and cpu.c, so apparently
we need this for KVM too
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/cpu-common.c | 43 +++++++++++++++++++++++++++++++++++++++++
target/arm/tcg/helper.c | 33 -------------------------------
2 files changed, 43 insertions(+), 33 deletions(-)
diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c
index 4f3cd84c02..b5cb3f9dae 100644
--- a/target/arm/cpu-common.c
+++ b/target/arm/cpu-common.c
@@ -221,3 +221,46 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
mask &= ~CACHED_CPSR_BITS;
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
}
+
+/*
+ * these are AARCH64-only, but due to the chain of dependencies,
+ * between HELPER prototypes, hflags, cpreg definitions and functions in
+ * tcg/ etc, it becomes incredibly messy to add what should be here:
+ *
+ * #ifdef TARGET_AARCH64
+ */
+
+static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
+{
+ uint32_t end_len;
+
+ end_len = start_len &= 0xf;
+ if (!test_bit(start_len, cpu->sve_vq_map)) {
+ end_len = find_last_bit(cpu->sve_vq_map, start_len);
+ assert(end_len < start_len);
+ }
+ return end_len;
+}
+
+/*
+ * Given that SVE is enabled, return the vector length for EL.
+ */
+uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
+{
+ ARMCPU *cpu = env_archcpu(env);
+ uint32_t zcr_len = cpu->sve_max_vq - 1;
+
+ if (el <= 1) {
+ zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
+ }
+ if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) {
+ zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
+ }
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
+ zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
+ }
+
+ return sve_zcr_get_valid_len(cpu, zcr_len);
+}
+
+/* #endif TARGET_AARCH64 , see matching comment above */
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index 9e6f21620e..430102e1ef 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -390,39 +390,6 @@ int sve_exception_el(CPUARMState *env, int el)
return 0;
}
-static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
-{
- uint32_t end_len;
-
- end_len = start_len &= 0xf;
- if (!test_bit(start_len, cpu->sve_vq_map)) {
- end_len = find_last_bit(cpu->sve_vq_map, start_len);
- assert(end_len < start_len);
- }
- return end_len;
-}
-
-/*
- * Given that SVE is enabled, return the vector length for EL.
- */
-uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
-{
- ARMCPU *cpu = env_archcpu(env);
- uint32_t zcr_len = cpu->sve_max_vq - 1;
-
- if (el <= 1) {
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
- }
- if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) {
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
- }
- if (arm_feature(env, ARM_FEATURE_EL3)) {
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
- }
-
- return sve_zcr_get_valid_len(cpu, zcr_len);
-}
-
void hw_watchpoint_update(ARMCPU *cpu, int n)
{
CPUARMState *env = &cpu->env;
--
2.26.2
next prev parent reply other threads:[~2021-03-03 11:47 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-03 11:40 [RFC v3 00/23] arm cleanup experiment for kvm-only build Claudio Fontana
2021-03-03 11:40 ` [RFC v3 01/23] target/arm: move translate modules to tcg/ Claudio Fontana
2021-03-03 11:40 ` [RFC v3 02/23] target/arm: move helpers " Claudio Fontana
2021-03-03 11:40 ` [RFC v3 03/23] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-03-03 11:40 ` [RFC v3 04/23] target/arm: tcg: add sysemu and user subsirs Claudio Fontana
2021-03-03 11:40 ` [RFC v3 05/23] target/arm: only build psci for TCG Claudio Fontana
2021-03-03 11:40 ` [RFC v3 06/23] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-03-03 11:40 ` [RFC v3 07/23] target/arm: move physical address translation to cpu-mmu Claudio Fontana
2021-03-03 11:40 ` [RFC v3 08/23] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-03-03 11:40 ` [RFC v3 09/23] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-03-03 11:40 ` [RFC v3 10/23] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-03-03 11:40 ` [RFC v3 11/23] target/arm: kvm: add stubs for some helpers Claudio Fontana
2021-03-03 11:40 ` [RFC v3 12/23] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-03-03 11:40 ` [RFC v3 13/23] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-03-03 11:40 ` [RFC v3 14/23] target/arm: split vfp state setting from tcg helpers Claudio Fontana
2021-03-03 11:40 ` [RFC v3 15/23] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-03-03 11:40 ` Claudio Fontana [this message]
2021-03-03 11:40 ` [RFC v3 17/23] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-03-03 11:40 ` [RFC v3 18/23] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-03-03 11:40 ` [RFC v3 19/23] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Claudio Fontana
2021-03-03 11:40 ` [RFC v3 20/23] target/arm: split 32bit cpu models from cpu.c to cpu32.c Claudio Fontana
2021-03-03 11:40 ` [RFC v3 21/23] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-03-03 11:40 ` [RFC v3 22/23] target/arm: move TCG cpu and models inside tcg/ Claudio Fontana
2021-03-03 11:40 ` [RFC v3 23/23] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
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