From: Claudio Fontana <cfontana@suse.de>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Roman Bolshakov <r.bolshakov@yadro.com>,
Claudio Fontana <cfontana@suse.de>,
Eduardo Habkost <ehabkost@redhat.com>,
qemu-devel@nongnu.org
Subject: [RFC v12 26/65] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code
Date: Fri, 26 Mar 2021 20:36:22 +0100 [thread overview]
Message-ID: <20210326193701.5981-27-cfontana@suse.de> (raw)
In-Reply-To: <20210326193701.5981-1-cfontana@suse.de>
and arm_phys_excp_target_el since it is tied up inside the
same #ifdef block.
aarch64_sync_32_to_64 and aarch64_sync_64_to_32 are
mixed in with the TCG helpers, but they shouldn't, as they
are needed for KVM too.
kvm_arch_get_registers()
{
if (!is_a64(env)) {
aarch64_sync_64_to_32(env);
}
write_kvmstate_to_list(cpu);
write_list_to_cpustate(cpu);
...
}
kvm_arch_put_registers()
{
if (!is_a64(env)) {
aarch64_sync_32_to_64(env);
}
write_cpustate_to_list(cpu, true);
write_list_to_kvmstate(cpu, level)
...
}
Move to the cpu module.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu-sysemu.c | 215 +++++++++++++++++++++++++++++++++++++
target/arm/cpu-user.c | 11 ++
target/arm/tcg/helper.c | 232 +---------------------------------------
3 files changed, 229 insertions(+), 229 deletions(-)
diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c
index 3add2c2439..7a314bf805 100644
--- a/target/arm/cpu-sysemu.c
+++ b/target/arm/cpu-sysemu.c
@@ -133,3 +133,218 @@ void switch_mode(CPUARMState *env, int mode)
env->banked_r14[r14_bank_number(old_mode)] = env->regs[14];
env->regs[14] = env->banked_r14[r14_bank_number(mode)];
}
+
+/*
+ * Function used to synchronize QEMU's AArch64 register set with AArch32
+ * register set. This is necessary when switching between AArch32 and AArch64
+ * execution state.
+ */
+void aarch64_sync_32_to_64(CPUARMState *env)
+{
+ int i;
+ uint32_t mode = env->uncached_cpsr & CPSR_M;
+
+ /* We can blanket copy R[0:7] to X[0:7] */
+ for (i = 0; i < 8; i++) {
+ env->xregs[i] = env->regs[i];
+ }
+
+ /*
+ * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
+ * Otherwise, they come from the banked user regs.
+ */
+ if (mode == ARM_CPU_MODE_FIQ) {
+ for (i = 8; i < 13; i++) {
+ env->xregs[i] = env->usr_regs[i - 8];
+ }
+ } else {
+ for (i = 8; i < 13; i++) {
+ env->xregs[i] = env->regs[i];
+ }
+ }
+
+ /*
+ * Registers x13-x23 are the various mode SP and FP registers. Registers
+ * r13 and r14 are only copied if we are in that mode, otherwise we copy
+ * from the mode banked register.
+ */
+ if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
+ env->xregs[13] = env->regs[13];
+ env->xregs[14] = env->regs[14];
+ } else {
+ env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
+ /* HYP is an exception in that it is copied from r14 */
+ if (mode == ARM_CPU_MODE_HYP) {
+ env->xregs[14] = env->regs[14];
+ } else {
+ env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)];
+ }
+ }
+
+ if (mode == ARM_CPU_MODE_HYP) {
+ env->xregs[15] = env->regs[13];
+ } else {
+ env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
+ }
+
+ if (mode == ARM_CPU_MODE_IRQ) {
+ env->xregs[16] = env->regs[14];
+ env->xregs[17] = env->regs[13];
+ } else {
+ env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)];
+ env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
+ }
+
+ if (mode == ARM_CPU_MODE_SVC) {
+ env->xregs[18] = env->regs[14];
+ env->xregs[19] = env->regs[13];
+ } else {
+ env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)];
+ env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
+ }
+
+ if (mode == ARM_CPU_MODE_ABT) {
+ env->xregs[20] = env->regs[14];
+ env->xregs[21] = env->regs[13];
+ } else {
+ env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)];
+ env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
+ }
+
+ if (mode == ARM_CPU_MODE_UND) {
+ env->xregs[22] = env->regs[14];
+ env->xregs[23] = env->regs[13];
+ } else {
+ env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)];
+ env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
+ }
+
+ /*
+ * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
+ * mode, then we can copy from r8-r14. Otherwise, we copy from the
+ * FIQ bank for r8-r14.
+ */
+ if (mode == ARM_CPU_MODE_FIQ) {
+ for (i = 24; i < 31; i++) {
+ env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */
+ }
+ } else {
+ for (i = 24; i < 29; i++) {
+ env->xregs[i] = env->fiq_regs[i - 24];
+ }
+ env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
+ env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)];
+ }
+
+ env->pc = env->regs[15];
+}
+
+/*
+ * Function used to synchronize QEMU's AArch32 register set with AArch64
+ * register set. This is necessary when switching between AArch32 and AArch64
+ * execution state.
+ */
+void aarch64_sync_64_to_32(CPUARMState *env)
+{
+ int i;
+ uint32_t mode = env->uncached_cpsr & CPSR_M;
+
+ /* We can blanket copy X[0:7] to R[0:7] */
+ for (i = 0; i < 8; i++) {
+ env->regs[i] = env->xregs[i];
+ }
+
+ /*
+ * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
+ * Otherwise, we copy x8-x12 into the banked user regs.
+ */
+ if (mode == ARM_CPU_MODE_FIQ) {
+ for (i = 8; i < 13; i++) {
+ env->usr_regs[i - 8] = env->xregs[i];
+ }
+ } else {
+ for (i = 8; i < 13; i++) {
+ env->regs[i] = env->xregs[i];
+ }
+ }
+
+ /*
+ * Registers r13 & r14 depend on the current mode.
+ * If we are in a given mode, we copy the corresponding x registers to r13
+ * and r14. Otherwise, we copy the x register to the banked r13 and r14
+ * for the mode.
+ */
+ if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
+ env->regs[13] = env->xregs[13];
+ env->regs[14] = env->xregs[14];
+ } else {
+ env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
+
+ /*
+ * HYP is an exception in that it does not have its own banked r14 but
+ * shares the USR r14
+ */
+ if (mode == ARM_CPU_MODE_HYP) {
+ env->regs[14] = env->xregs[14];
+ } else {
+ env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
+ }
+ }
+
+ if (mode == ARM_CPU_MODE_HYP) {
+ env->regs[13] = env->xregs[15];
+ } else {
+ env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
+ }
+
+ if (mode == ARM_CPU_MODE_IRQ) {
+ env->regs[14] = env->xregs[16];
+ env->regs[13] = env->xregs[17];
+ } else {
+ env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
+ env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
+ }
+
+ if (mode == ARM_CPU_MODE_SVC) {
+ env->regs[14] = env->xregs[18];
+ env->regs[13] = env->xregs[19];
+ } else {
+ env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
+ env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
+ }
+
+ if (mode == ARM_CPU_MODE_ABT) {
+ env->regs[14] = env->xregs[20];
+ env->regs[13] = env->xregs[21];
+ } else {
+ env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
+ env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
+ }
+
+ if (mode == ARM_CPU_MODE_UND) {
+ env->regs[14] = env->xregs[22];
+ env->regs[13] = env->xregs[23];
+ } else {
+ env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
+ env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
+ }
+
+ /*
+ * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
+ * mode, then we can copy to r8-r14. Otherwise, we copy to the
+ * FIQ bank for r8-r14.
+ */
+ if (mode == ARM_CPU_MODE_FIQ) {
+ for (i = 24; i < 31; i++) {
+ env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */
+ }
+ } else {
+ for (i = 24; i < 29; i++) {
+ env->fiq_regs[i - 24] = env->xregs[i];
+ }
+ env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
+ env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
+ }
+
+ env->regs[15] = env->pc;
+}
diff --git a/target/arm/cpu-user.c b/target/arm/cpu-user.c
index a72b7f5703..0225089e46 100644
--- a/target/arm/cpu-user.c
+++ b/target/arm/cpu-user.c
@@ -22,3 +22,14 @@ void switch_mode(CPUARMState *env, int mode)
cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
}
}
+
+void aarch64_sync_64_to_32(CPUARMState *env)
+{
+ g_assert_not_reached();
+}
+
+uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
+ uint32_t cur_el, bool secure)
+{
+ return 1;
+}
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index 9763cae8f8..5ec8f9c005 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -590,22 +590,10 @@ uint32_t HELPER(rbit)(uint32_t x)
return revbit32(x);
}
-#ifdef CONFIG_USER_ONLY
+#ifndef CONFIG_USER_ONLY
-uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
- uint32_t cur_el, bool secure)
-{
- return 1;
-}
-
-void aarch64_sync_64_to_32(CPUARMState *env)
-{
- g_assert_not_reached();
-}
-
-#else
-
-/* Physical Interrupt Target EL Lookup Table
+/*
+ * Physical Interrupt Target EL Lookup Table
*
* [ From ARM ARM section G1.13.4 (Table G1-15) ]
*
@@ -754,220 +742,6 @@ void arm_log_exception(int idx)
}
}
-/*
- * Function used to synchronize QEMU's AArch64 register set with AArch32
- * register set. This is necessary when switching between AArch32 and AArch64
- * execution state.
- */
-void aarch64_sync_32_to_64(CPUARMState *env)
-{
- int i;
- uint32_t mode = env->uncached_cpsr & CPSR_M;
-
- /* We can blanket copy R[0:7] to X[0:7] */
- for (i = 0; i < 8; i++) {
- env->xregs[i] = env->regs[i];
- }
-
- /*
- * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
- * Otherwise, they come from the banked user regs.
- */
- if (mode == ARM_CPU_MODE_FIQ) {
- for (i = 8; i < 13; i++) {
- env->xregs[i] = env->usr_regs[i - 8];
- }
- } else {
- for (i = 8; i < 13; i++) {
- env->xregs[i] = env->regs[i];
- }
- }
-
- /*
- * Registers x13-x23 are the various mode SP and FP registers. Registers
- * r13 and r14 are only copied if we are in that mode, otherwise we copy
- * from the mode banked register.
- */
- if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
- env->xregs[13] = env->regs[13];
- env->xregs[14] = env->regs[14];
- } else {
- env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
- /* HYP is an exception in that it is copied from r14 */
- if (mode == ARM_CPU_MODE_HYP) {
- env->xregs[14] = env->regs[14];
- } else {
- env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)];
- }
- }
-
- if (mode == ARM_CPU_MODE_HYP) {
- env->xregs[15] = env->regs[13];
- } else {
- env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
- }
-
- if (mode == ARM_CPU_MODE_IRQ) {
- env->xregs[16] = env->regs[14];
- env->xregs[17] = env->regs[13];
- } else {
- env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)];
- env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
- }
-
- if (mode == ARM_CPU_MODE_SVC) {
- env->xregs[18] = env->regs[14];
- env->xregs[19] = env->regs[13];
- } else {
- env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)];
- env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
- }
-
- if (mode == ARM_CPU_MODE_ABT) {
- env->xregs[20] = env->regs[14];
- env->xregs[21] = env->regs[13];
- } else {
- env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)];
- env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
- }
-
- if (mode == ARM_CPU_MODE_UND) {
- env->xregs[22] = env->regs[14];
- env->xregs[23] = env->regs[13];
- } else {
- env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)];
- env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
- }
-
- /*
- * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
- * mode, then we can copy from r8-r14. Otherwise, we copy from the
- * FIQ bank for r8-r14.
- */
- if (mode == ARM_CPU_MODE_FIQ) {
- for (i = 24; i < 31; i++) {
- env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */
- }
- } else {
- for (i = 24; i < 29; i++) {
- env->xregs[i] = env->fiq_regs[i - 24];
- }
- env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
- env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)];
- }
-
- env->pc = env->regs[15];
-}
-
-/*
- * Function used to synchronize QEMU's AArch32 register set with AArch64
- * register set. This is necessary when switching between AArch32 and AArch64
- * execution state.
- */
-void aarch64_sync_64_to_32(CPUARMState *env)
-{
- int i;
- uint32_t mode = env->uncached_cpsr & CPSR_M;
-
- /* We can blanket copy X[0:7] to R[0:7] */
- for (i = 0; i < 8; i++) {
- env->regs[i] = env->xregs[i];
- }
-
- /*
- * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
- * Otherwise, we copy x8-x12 into the banked user regs.
- */
- if (mode == ARM_CPU_MODE_FIQ) {
- for (i = 8; i < 13; i++) {
- env->usr_regs[i - 8] = env->xregs[i];
- }
- } else {
- for (i = 8; i < 13; i++) {
- env->regs[i] = env->xregs[i];
- }
- }
-
- /*
- * Registers r13 & r14 depend on the current mode.
- * If we are in a given mode, we copy the corresponding x registers to r13
- * and r14. Otherwise, we copy the x register to the banked r13 and r14
- * for the mode.
- */
- if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
- env->regs[13] = env->xregs[13];
- env->regs[14] = env->xregs[14];
- } else {
- env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
-
- /*
- * HYP is an exception in that it does not have its own banked r14 but
- * shares the USR r14
- */
- if (mode == ARM_CPU_MODE_HYP) {
- env->regs[14] = env->xregs[14];
- } else {
- env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
- }
- }
-
- if (mode == ARM_CPU_MODE_HYP) {
- env->regs[13] = env->xregs[15];
- } else {
- env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
- }
-
- if (mode == ARM_CPU_MODE_IRQ) {
- env->regs[14] = env->xregs[16];
- env->regs[13] = env->xregs[17];
- } else {
- env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
- env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
- }
-
- if (mode == ARM_CPU_MODE_SVC) {
- env->regs[14] = env->xregs[18];
- env->regs[13] = env->xregs[19];
- } else {
- env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
- env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
- }
-
- if (mode == ARM_CPU_MODE_ABT) {
- env->regs[14] = env->xregs[20];
- env->regs[13] = env->xregs[21];
- } else {
- env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
- env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
- }
-
- if (mode == ARM_CPU_MODE_UND) {
- env->regs[14] = env->xregs[22];
- env->regs[13] = env->xregs[23];
- } else {
- env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
- env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
- }
-
- /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
- * mode, then we can copy to r8-r14. Otherwise, we copy to the
- * FIQ bank for r8-r14.
- */
- if (mode == ARM_CPU_MODE_FIQ) {
- for (i = 24; i < 31; i++) {
- env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */
- }
- } else {
- for (i = 24; i < 29; i++) {
- env->fiq_regs[i - 24] = env->xregs[i];
- }
- env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
- env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
- }
-
- env->regs[15] = env->pc;
-}
-
static void take_aarch32_exception(CPUARMState *env, int new_mode,
uint32_t mask, uint32_t offset,
uint32_t newpc)
--
2.26.2
next prev parent reply other threads:[~2021-03-26 19:46 UTC|newest]
Thread overview: 145+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-26 19:35 [RFC v12 00/65] arm cleanup experiment for kvm-only build Claudio Fontana
2021-03-26 19:35 ` [RFC v12 01/65] target/arm: move translate modules to tcg/ Claudio Fontana
2021-03-26 19:35 ` [RFC v12 02/65] target/arm: move helpers " Claudio Fontana
2021-03-26 19:35 ` [RFC v12 03/65] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-04-13 20:49 ` Philippe Mathieu-Daudé
2021-04-14 8:28 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 04/65] target/arm: tcg: add sysemu and user subdirs Claudio Fontana
2021-03-28 15:42 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 05/65] target/arm: tcg: split mte_helper user-only and sysemu code Claudio Fontana
2021-04-08 14:41 ` Alex Bennée
2021-04-08 15:56 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 06/65] target/arm: tcg: move sysemu-only parts of debug_helper Claudio Fontana
2021-04-08 14:47 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 07/65] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Claudio Fontana
2021-04-08 14:20 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 08/65] target/arm: tcg: split m_helper " Claudio Fontana
2021-04-08 17:34 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 09/65] target/arm: only build psci for TCG Claudio Fontana
2021-03-28 15:43 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 10/65] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-03-26 19:36 ` [RFC v12 11/65] target/arm: tcg: fix comment style before move to cpu-mmu Claudio Fontana
2021-03-28 15:44 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 12/65] target/arm: move physical address translation " Claudio Fontana
2021-04-12 14:13 ` Alex Bennée
2021-03-26 19:36 ` [RFC v12 13/65] target/arm: fix style in preparation of new cpregs module Claudio Fontana
2021-03-28 15:45 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 14/65] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-03-28 15:49 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 15/65] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-03-26 19:36 ` [RFC v12 16/65] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-03-26 19:36 ` [RFC v12 17/65] target/arm: tcg: add stubs for some helpers for non-tcg builds Claudio Fontana
2021-03-28 15:51 ` Richard Henderson
2021-03-28 16:22 ` Richard Henderson
2021-04-08 10:39 ` Claudio Fontana
2021-04-08 14:35 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 18/65] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-03-28 15:54 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 19/65] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-03-28 15:57 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 20/65] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu Claudio Fontana
2021-03-28 16:05 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 21/65] target/arm: split vfp state setting from tcg helpers Claudio Fontana
2021-03-28 16:10 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 22/65] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-03-26 19:36 ` [RFC v12 23/65] target/arm: move sve_zcr_len_for_el to common_cpu Claudio Fontana
2021-03-26 19:36 ` [RFC v12 24/65] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-03-28 16:12 ` Richard Henderson
2021-04-08 9:55 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 25/65] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-03-26 19:36 ` Claudio Fontana [this message]
2021-03-26 19:36 ` [RFC v12 27/65] target/arm: split a15 cpu model and 32bit class functions to cpu32.c Claudio Fontana
2021-03-28 16:18 ` Richard Henderson
2021-04-08 10:23 ` Claudio Fontana
2021-04-08 10:36 ` Peter Maydell
2021-04-12 9:05 ` Claudio Fontana
2021-04-12 9:10 ` Peter Maydell
2021-04-13 8:32 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 28/65] target/arm: fixup sve_exception_el code style before move Claudio Fontana
2021-03-28 16:19 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 29/65] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-03-26 19:36 ` [RFC v12 30/65] target/arm: fix style of arm_cpu_do_interrupt functions before move Claudio Fontana
2021-03-28 16:24 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 31/65] target/arm: move exception code out of tcg/helper.c Claudio Fontana
2021-03-28 16:40 ` Richard Henderson
2021-04-08 10:56 ` Claudio Fontana
2021-04-08 15:05 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 32/65] target/arm: move TCGCPUOps to tcg/tcg-cpu.c Claudio Fontana
2021-03-28 16:48 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 33/65] target/arm: move cpu_tcg to tcg/tcg-cpu-models.c Claudio Fontana
2021-03-28 16:52 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 34/65] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
2021-03-26 19:36 ` [RFC v12 35/65] target/arm: remove kvm include file for PSCI and arm-powerctl Claudio Fontana
2021-03-26 19:36 ` [RFC v12 36/65] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Claudio Fontana
2021-03-28 16:54 ` Richard Henderson
2021-03-28 16:56 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 37/65] target/arm: cleanup cpu includes Claudio Fontana
2021-03-28 16:58 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 38/65] target/arm: remove broad "else" statements when checking accels Claudio Fontana
2021-03-28 17:11 ` Richard Henderson
2021-03-29 6:58 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 39/65] target/arm: remove kvm-stub.c Claudio Fontana
2021-03-28 17:12 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 40/65] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Claudio Fontana
2021-03-28 17:21 ` Richard Henderson
2021-03-29 7:02 ` Claudio Fontana
2021-03-29 14:03 ` Richard Henderson
2021-04-08 13:24 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 41/65] tests: restrict TCG-only arm-cpu-features tests to TCG builds Claudio Fontana
2021-03-28 17:23 ` Richard Henderson
2021-04-08 13:30 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 42/65] tests: do not run test-hmp on all machines for ARM KVM-only Claudio Fontana
2021-03-28 17:24 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 43/65] tests: device-introspect-test: cope with ARM TCG-only devices Claudio Fontana
2021-03-28 17:25 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 44/65] tests: do not run qom-test on all machines for ARM KVM-only Claudio Fontana
2021-03-28 17:26 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 45/65] Revert "target/arm: Restrict v8M IDAU to TCG" Claudio Fontana
2021-03-28 17:40 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 46/65] target/arm: create kvm cpu accel class Claudio Fontana
2021-03-28 17:46 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 47/65] target/arm: move kvm post init initialization to kvm cpu accel Claudio Fontana
2021-03-28 17:49 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 48/65] target/arm: add tcg cpu accel class Claudio Fontana
2021-03-28 17:51 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 49/65] target/arm: move TCG gt timer creation code in tcg/ Claudio Fontana
2021-03-28 17:54 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 50/65] target/arm: cpu-sve: new module Claudio Fontana
2021-03-28 18:05 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 51/65] target/arm: cpu-sve: split TCG and KVM functionality Claudio Fontana
2021-03-28 18:21 ` Richard Henderson
2021-04-08 14:28 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 52/65] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Claudio Fontana
2021-03-28 18:31 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 53/65] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64 Claudio Fontana
2021-03-28 18:34 ` Richard Henderson
2021-03-28 19:02 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 54/65] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Claudio Fontana
2021-03-28 18:36 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 55/65] target/arm: cpu-exceptions: new module Claudio Fontana
2021-03-28 18:40 ` Richard Henderson
2021-04-12 11:53 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 56/65] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Claudio Fontana
2021-03-28 18:47 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 57/65] target/arm: tcg-sve: import narrow_vq and change_el functions Claudio Fontana
2021-03-28 18:51 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 58/65] target/arm: tcg-sve: rename the " Claudio Fontana
2021-03-28 18:55 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 59/65] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve Claudio Fontana
2021-03-28 19:03 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 60/65] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Claudio Fontana
2021-03-28 19:05 ` Richard Henderson
2021-04-13 12:16 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 61/65] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el Claudio Fontana
2021-03-28 19:09 ` Richard Henderson
2021-03-26 19:36 ` [RFC v12 62/65] target/arm: refactor arm_cpu_finalize_features into cpu64 Claudio Fontana
2021-03-28 19:12 ` Richard Henderson
2021-03-28 19:15 ` Richard Henderson
2021-04-13 17:14 ` Claudio Fontana
2021-03-26 19:36 ` [RFC v12 63/65] XXX target/arm: experiment refactoring cpu "max" Claudio Fontana
2021-03-26 19:37 ` [RFC v12 64/65] target/arm: tcg: remove superfluous CONFIG_TCG check Claudio Fontana
2021-03-28 19:16 ` Richard Henderson
2021-03-26 19:37 ` [RFC v12 65/65] target/arm: remove v7m stub function for !CONFIG_TCG Claudio Fontana
2021-03-28 19:17 ` Richard Henderson
2021-03-28 19:27 ` [RFC v12 00/65] arm cleanup experiment for kvm-only build Richard Henderson
2021-04-13 12:05 ` Claudio Fontana
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