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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-arm@nongnu.org
Subject: [PATCH v5 15/31] target/arm: Enforce word alignment for LDRD/STRD
Date: Mon, 19 Apr 2021 13:22:41 -0700	[thread overview]
Message-ID: <20210419202257.161730-16-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210419202257.161730-1-richard.henderson@linaro.org>

Buglink: https://bugs.launchpad.net/qemu/+bug/1905356
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6171347d6d..1b0951c45b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6512,13 +6512,13 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
     addr = op_addr_rr_pre(s, a);
 
     tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     store_reg(s, a->rt, tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
 
     tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     store_reg(s, a->rt + 1, tmp);
 
     /* LDRD w/ base writeback is undefined if the registers overlap.  */
@@ -6541,13 +6541,13 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
     addr = op_addr_rr_pre(s, a);
 
     tmp = load_reg(s, a->rt);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     tcg_temp_free_i32(tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
 
     tmp = load_reg(s, a->rt + 1);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     tcg_temp_free_i32(tmp);
 
     op_addr_rr_post(s, a, addr, -4);
@@ -6649,13 +6649,13 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
     addr = op_addr_ri_pre(s, a);
 
     tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     store_reg(s, a->rt, tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
 
     tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     store_reg(s, rt2, tmp);
 
     /* LDRD w/ base writeback is undefined if the registers overlap.  */
@@ -6688,13 +6688,13 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
     addr = op_addr_ri_pre(s, a);
 
     tmp = load_reg(s, a->rt);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     tcg_temp_free_i32(tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
 
     tmp = load_reg(s, rt2);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
     tcg_temp_free_i32(tmp);
 
     op_addr_ri_post(s, a, addr, -4);
-- 
2.25.1



  parent reply	other threads:[~2021-04-19 20:41 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
2021-04-19 20:22 ` [PATCH v5 01/31] target/arm: Fix decode of align in VLDST_single Richard Henderson
2021-04-19 20:22 ` [PATCH v5 02/31] target/arm: Rename TBFLAG_A32, SCTLR_B Richard Henderson
2021-04-19 20:22 ` [PATCH v5 03/31] target/arm: Rename TBFLAG_ANY, PSTATE_SS Richard Henderson
2021-04-19 20:22 ` [PATCH v5 04/31] target/arm: Add wrapper macros for accessing tbflags Richard Henderson
2021-04-19 20:22 ` [PATCH v5 05/31] target/arm: Introduce CPUARMTBFlags Richard Henderson
2021-04-19 20:22 ` [PATCH v5 06/31] target/arm: Move mode specific TB flags to tb->cs_base Richard Henderson
2021-04-19 20:22 ` [PATCH v5 07/31] target/arm: Use cpu_abort in assert_hflags_rebuild_correctly Richard Henderson
2021-04-20  9:07   ` Peter Maydell
2021-04-19 20:22 ` [PATCH v5 08/31] target/arm: Move TBFLAG_AM32 bits to the top Richard Henderson
2021-04-19 20:22 ` [PATCH v5 09/31] target/arm: Move TBFLAG_ANY bits to the bottom Richard Henderson
2021-04-19 20:22 ` [PATCH v5 10/31] target/arm: Add ALIGN_MEM to TBFLAG_ANY Richard Henderson
2021-04-19 20:22 ` [PATCH v5 11/31] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Richard Henderson
2021-04-19 20:22 ` [PATCH v5 12/31] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Richard Henderson
2021-04-19 20:22 ` [PATCH v5 13/31] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Richard Henderson
2021-04-19 20:22 ` [PATCH v5 14/31] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Richard Henderson
2021-04-19 20:22 ` Richard Henderson [this message]
2021-04-19 20:22 ` [PATCH v5 16/31] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
2021-04-19 20:22 ` [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM Richard Henderson
2021-08-31  0:51   ` Nathan Chancellor
2021-09-07 13:44     ` Richard Henderson
2021-09-15  1:13       ` Nick Desaulniers
2021-04-19 20:22 ` [PATCH v5 18/31] target/arm: Enforce alignment for RFE Richard Henderson
2021-04-19 20:22 ` [PATCH v5 19/31] target/arm: Enforce alignment for SRS Richard Henderson
2021-04-19 20:22 ` [PATCH v5 20/31] target/arm: Enforce alignment for VLDM/VSTM Richard Henderson
2021-04-19 20:22 ` [PATCH v5 21/31] target/arm: Enforce alignment for VLDR/VSTR Richard Henderson
2021-04-19 20:22 ` [PATCH v5 22/31] target/arm: Enforce alignment for VLDn (all lanes) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 23/31] target/arm: Enforce alignment for VLDn/VSTn (multiple) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 24/31] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 25/31] target/arm: Use finalize_memop for aa64 gpr load/store Richard Henderson
2021-04-19 20:22 ` [PATCH v5 26/31] target/arm: Use finalize_memop for aa64 fpr load/store Richard Henderson
2021-04-19 20:22 ` [PATCH v5 27/31] target/arm: Enforce alignment for aa64 load-acq/store-rel Richard Henderson
2021-04-19 20:22 ` [PATCH v5 28/31] target/arm: Use MemOp for size + endian in aa64 vector ld/st Richard Henderson
2021-04-19 20:22 ` [PATCH v5 29/31] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 30/31] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 31/31] target/arm: Enforce alignment for sve LD1R Richard Henderson
2021-04-20 10:27 ` [PATCH v5 00/31] target/arm: enforce alignment Peter Maydell

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