From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>,
Frank Chang <frank.chang@sifive.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Kito Cheng <kito.cheng@sifive.com>
Subject: [PATCH v5 04/17] target/riscv: rvb: logic-with-negate
Date: Wed, 21 Apr 2021 12:13:46 +0800 [thread overview]
Message-ID: <20210421041400.22243-5-frank.chang@sifive.com> (raw)
In-Reply-To: <20210421041400.22243-1-frank.chang@sifive.com>
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 18 ++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0e321da37f4..d0b3f109b4e 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -598,3 +598,7 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
cpop 011000 000010 ..... 001 ..... 0010011 @r2
+
+andn 0100000 .......... 111 ..... 0110011 @r
+orn 0100000 .......... 110 ..... 0110011 @r
+xnor 0100000 .......... 100 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index dbbd94e1015..73c4693a263 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -35,6 +35,24 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
return gen_unary(ctx, a, tcg_gen_ctpop_tl);
}
+static bool trans_andn(DisasContext *ctx, arg_andn *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_andc_tl);
+}
+
+static bool trans_orn(DisasContext *ctx, arg_orn *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_orc_tl);
+}
+
+static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, tcg_gen_eqv_tl);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
--
2.17.1
next prev parent reply other threads:[~2021-04-21 4:18 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-21 4:13 [PATCH v5 00/17] support subsets of bitmanip extension frank.chang
2021-04-21 4:13 ` [PATCH v5 01/17] target/riscv: reformat @sh format encoding for B-extension frank.chang
2021-04-21 4:13 ` [PATCH v5 02/17] target/riscv: rvb: count leading/trailing zeros frank.chang
2021-04-27 6:01 ` Alistair Francis
2021-04-27 7:13 ` Frank Chang
2021-04-21 4:13 ` [PATCH v5 03/17] target/riscv: rvb: count bits set frank.chang
2021-04-27 6:03 ` Alistair Francis
2021-04-21 4:13 ` frank.chang [this message]
2021-04-27 6:04 ` [PATCH v5 04/17] target/riscv: rvb: logic-with-negate Alistair Francis
2021-04-21 4:13 ` [PATCH v5 05/17] target/riscv: rvb: pack two words into one register frank.chang
2021-04-27 6:05 ` Alistair Francis
2021-04-21 4:13 ` [PATCH v5 06/17] target/riscv: rvb: min/max instructions frank.chang
2021-04-27 6:06 ` Alistair Francis
2021-04-21 4:13 ` [PATCH v5 07/17] target/riscv: rvb: sign-extend instructions frank.chang
2021-04-27 6:06 ` Alistair Francis
2021-04-21 4:13 ` [PATCH v5 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions frank.chang
2021-04-21 4:13 ` [PATCH v5 09/17] target/riscv: rvb: single-bit instructions frank.chang
2021-04-21 4:13 ` [PATCH v5 10/17] target/riscv: rvb: shift ones frank.chang
2021-04-21 4:13 ` [PATCH v5 11/17] target/riscv: rvb: rotate (left/right) frank.chang
2021-04-21 4:13 ` [PATCH v5 12/17] target/riscv: rvb: generalized reverse frank.chang
2021-04-21 4:13 ` [PATCH v5 13/17] target/riscv: rvb: generalized or-combine frank.chang
2021-04-21 4:13 ` [PATCH v5 14/17] target/riscv: rvb: address calculation frank.chang
2021-04-21 4:13 ` [PATCH v5 15/17] target/riscv: rvb: add/shift with prefix zero-extend frank.chang
2021-04-21 4:13 ` [PATCH v5 16/17] target/riscv: rvb: support and turn on B-extension from command line frank.chang
2021-04-21 4:13 ` [PATCH v5 17/17] target/riscv: rvb: add b-ext version cpu option frank.chang
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