From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH v6 30/82] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS
Date: Fri, 30 Apr 2021 13:25:18 -0700 [thread overview]
Message-ID: <20210430202610.1136687-31-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210430202610.1136687-1-richard.henderson@linaro.org>
Rename the existing sve_while (less-than) helper to sve_whilel
to make room for a new sve_whileg helper for greater-than.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Use a new helper function to implement this.
v4: Update for PREDDESC.
---
target/arm/helper-sve.h | 3 +-
target/arm/sve.decode | 2 +-
target/arm/sve_helper.c | 38 +++++++++++++++++++++++++-
target/arm/translate-sve.c | 56 ++++++++++++++++++++++++++++----------
4 files changed, 82 insertions(+), 17 deletions(-)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 1c7fe8e417..5bf9fdc7a3 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -913,7 +913,8 @@ DEF_HELPER_FLAGS_4(sve_brkns, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_cntp, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
-DEF_HELPER_FLAGS_3(sve_while, TCG_CALL_NO_RWG, i32, ptr, i32, i32)
+DEF_HELPER_FLAGS_3(sve_whilel, TCG_CALL_NO_RWG, i32, ptr, i32, i32)
+DEF_HELPER_FLAGS_3(sve_whileg, TCG_CALL_NO_RWG, i32, ptr, i32, i32)
DEF_HELPER_FLAGS_4(sve_subri_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(sve_subri_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 0674464695..ae853d21f2 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -700,7 +700,7 @@ SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred
CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000
# SVE integer compare scalar count and limit
-WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4
+WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 lt:1 rn:5 eq:1 rd:4
### SVE Integer Wide Immediate - Unpredicated Group
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 02e87c535d..fb38f2c57e 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -3745,7 +3745,7 @@ uint64_t HELPER(sve_cntp)(void *vn, void *vg, uint32_t pred_desc)
return sum;
}
-uint32_t HELPER(sve_while)(void *vd, uint32_t count, uint32_t pred_desc)
+uint32_t HELPER(sve_whilel)(void *vd, uint32_t count, uint32_t pred_desc)
{
intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
intptr_t esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
@@ -3771,6 +3771,42 @@ uint32_t HELPER(sve_while)(void *vd, uint32_t count, uint32_t pred_desc)
return predtest_ones(d, oprsz, esz_mask);
}
+uint32_t HELPER(sve_whileg)(void *vd, uint32_t count, uint32_t pred_desc)
+{
+ intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ);
+ intptr_t esz = FIELD_EX32(pred_desc, PREDDESC, ESZ);
+ uint64_t esz_mask = pred_esz_masks[esz];
+ ARMPredicateReg *d = vd;
+ intptr_t i, invcount, oprbits;
+ uint64_t bits;
+
+ if (count == 0) {
+ return do_zero(d, oprsz);
+ }
+
+ oprbits = oprsz * 8;
+ tcg_debug_assert(count <= oprbits);
+
+ bits = esz_mask;
+ if (oprbits & 63) {
+ bits &= MAKE_64BIT_MASK(0, oprbits & 63);
+ }
+
+ invcount = oprbits - count;
+ for (i = (oprsz - 1) / 8; i > invcount / 64; --i) {
+ d->p[i] = bits;
+ bits = esz_mask;
+ }
+
+ d->p[i] = bits & MAKE_64BIT_MASK(invcount & 63, 64);
+
+ while (--i >= 0) {
+ d->p[i] = 0;
+ }
+
+ return predtest_ones(d, oprsz, esz_mask);
+}
+
/* Recursive reduction on a function;
* C.f. the ARM ARM function ReducePredicated.
*
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 218f1ca5ce..aff85b0220 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3112,7 +3112,14 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
unsigned vsz = vec_full_reg_size(s);
unsigned desc = 0;
TCGCond cond;
+ uint64_t maxval;
+ /* Note that GE/HS has a->eq == 0 and GT/HI has a->eq == 1. */
+ bool eq = a->eq == a->lt;
+ /* The greater-than conditions are all SVE2. */
+ if (!a->lt && !dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
if (!sve_access_check(s)) {
return true;
}
@@ -3135,22 +3142,42 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
*/
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
- tcg_gen_sub_i64(t0, op1, op0);
+
+ if (a->lt) {
+ tcg_gen_sub_i64(t0, op1, op0);
+ if (a->u) {
+ maxval = a->sf ? UINT64_MAX : UINT32_MAX;
+ cond = eq ? TCG_COND_LEU : TCG_COND_LTU;
+ } else {
+ maxval = a->sf ? INT64_MAX : INT32_MAX;
+ cond = eq ? TCG_COND_LE : TCG_COND_LT;
+ }
+ } else {
+ tcg_gen_sub_i64(t0, op0, op1);
+ if (a->u) {
+ maxval = 0;
+ cond = eq ? TCG_COND_GEU : TCG_COND_GTU;
+ } else {
+ maxval = a->sf ? INT64_MIN : INT32_MIN;
+ cond = eq ? TCG_COND_GE : TCG_COND_GT;
+ }
+ }
tmax = tcg_const_i64(vsz >> a->esz);
- if (a->eq) {
+ if (eq) {
/* Equality means one more iteration. */
tcg_gen_addi_i64(t0, t0, 1);
- /* If op1 is max (un)signed integer (and the only time the addition
- * above could overflow), then we produce an all-true predicate by
- * setting the count to the vector length. This is because the
- * pseudocode is described as an increment + compare loop, and the
- * max integer would always compare true.
+ /*
+ * For the less-than while, if op1 is maxval (and the only time
+ * the addition above could overflow), then we produce an all-true
+ * predicate by setting the count to the vector length. This is
+ * because the pseudocode is described as an increment + compare
+ * loop, and the maximum integer would always compare true.
+ * Similarly, the greater-than while has the same issue with the
+ * minimum integer due to the decrement + compare loop.
*/
- tcg_gen_movi_i64(t1, (a->sf
- ? (a->u ? UINT64_MAX : INT64_MAX)
- : (a->u ? UINT32_MAX : INT32_MAX)));
+ tcg_gen_movi_i64(t1, maxval);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, op1, t1, tmax, t0);
}
@@ -3159,9 +3186,6 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
tcg_temp_free_i64(tmax);
/* Set the count to zero if the condition is false. */
- cond = (a->u
- ? (a->eq ? TCG_COND_LEU : TCG_COND_LTU)
- : (a->eq ? TCG_COND_LE : TCG_COND_LT));
tcg_gen_movi_i64(t1, 0);
tcg_gen_movcond_i64(cond, t0, op0, op1, t0, t1);
tcg_temp_free_i64(t1);
@@ -3181,7 +3205,11 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a)
ptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd));
- gen_helper_sve_while(t2, ptr, t2, t3);
+ if (a->lt) {
+ gen_helper_sve_whilel(t2, ptr, t2, t3);
+ } else {
+ gen_helper_sve_whileg(t2, ptr, t2, t3);
+ }
do_pred_flags(t2);
tcg_temp_free_ptr(ptr);
--
2.25.1
next prev parent reply other threads:[~2021-04-30 20:55 UTC|newest]
Thread overview: 184+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-30 20:24 [PATCH v6 00/82] target/arm: Implement SVE2 Richard Henderson
2021-04-30 20:24 ` [PATCH v6 01/82] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 Richard Henderson
2021-05-11 7:55 ` Peter Maydell
2021-05-11 17:20 ` Richard Henderson
2021-04-30 20:24 ` [PATCH v6 02/82] target/arm: Implement SVE2 Integer Multiply - Unpredicated Richard Henderson
2021-05-11 8:00 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 03/82] target/arm: Implement SVE2 integer pairwise add and accumulate long Richard Henderson
2021-05-11 8:02 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 04/82] target/arm: Implement SVE2 integer unary operations (predicated) Richard Henderson
2021-05-11 8:10 ` Peter Maydell
2021-05-11 17:22 ` Richard Henderson
2021-04-30 20:24 ` [PATCH v6 05/82] target/arm: Split out saturating/rounding shifts from neon Richard Henderson
2021-05-11 8:36 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 06/82] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated) Richard Henderson
2021-05-11 8:43 ` Peter Maydell
2021-05-11 15:40 ` Richard Henderson
2021-05-11 15:56 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 07/82] target/arm: Implement SVE2 integer halving add/subtract (predicated) Richard Henderson
2021-05-11 8:45 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 08/82] target/arm: Implement SVE2 integer pairwise arithmetic Richard Henderson
2021-05-11 8:58 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 09/82] target/arm: Implement SVE2 saturating add/subtract (predicated) Richard Henderson
2021-05-11 9:07 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 10/82] target/arm: Implement SVE2 integer add/subtract long Richard Henderson
2021-05-11 9:11 ` Peter Maydell
2021-04-30 20:24 ` [PATCH v6 11/82] target/arm: Implement SVE2 integer add/subtract interleaved long Richard Henderson
2021-05-11 9:12 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 12/82] target/arm: Implement SVE2 integer add/subtract wide Richard Henderson
2021-05-11 9:14 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 13/82] target/arm: Implement SVE2 integer multiply long Richard Henderson
2021-05-11 12:21 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 14/82] target/arm: Implement PMULLB and PMULLT Richard Henderson
2021-05-11 12:29 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 15/82] target/arm: Implement SVE2 bitwise shift left long Richard Henderson
2021-05-11 12:40 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 16/82] target/arm: Implement SVE2 bitwise exclusive-or interleaved Richard Henderson
2021-05-11 12:43 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 17/82] target/arm: Implement SVE2 bitwise permute Richard Henderson
2021-05-11 12:58 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 18/82] target/arm: Implement SVE2 complex integer add Richard Henderson
2021-05-11 13:02 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 19/82] target/arm: Implement SVE2 integer absolute difference and accumulate long Richard Henderson
2021-05-11 15:27 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 20/82] target/arm: Implement SVE2 integer add/subtract long with carry Richard Henderson
2021-05-11 15:48 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 21/82] target/arm: Implement SVE2 bitwise shift right and accumulate Richard Henderson
2021-05-11 15:57 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 22/82] target/arm: Implement SVE2 bitwise shift and insert Richard Henderson
2021-05-11 15:58 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 23/82] target/arm: Implement SVE2 integer absolute difference and accumulate Richard Henderson
2021-05-11 15:59 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 24/82] target/arm: Implement SVE2 saturating extract narrow Richard Henderson
2021-05-11 16:08 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 25/82] target/arm: Implement SVE2 floating-point pairwise Richard Henderson
2021-05-11 16:09 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 26/82] target/arm: Implement SVE2 SHRN, RSHRN Richard Henderson
2021-05-12 8:52 ` Peter Maydell
2021-05-12 16:07 ` Richard Henderson
2021-04-30 20:25 ` [PATCH v6 27/82] target/arm: Implement SVE2 SQSHRUN, SQRSHRUN Richard Henderson
2021-05-12 8:54 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 28/82] target/arm: Implement SVE2 UQSHRN, UQRSHRN Richard Henderson
2021-05-12 8:56 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 29/82] target/arm: Implement SVE2 SQSHRN, SQRSHRN Richard Henderson
2021-05-12 8:59 ` Peter Maydell
2021-04-30 20:25 ` Richard Henderson [this message]
2021-05-12 9:07 ` [PATCH v6 30/82] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS Peter Maydell
2021-04-30 20:25 ` [PATCH v6 31/82] target/arm: Implement SVE2 WHILERW, WHILEWR Richard Henderson
2021-05-12 14:06 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 32/82] target/arm: Implement SVE2 bitwise ternary operations Richard Henderson
2021-05-12 14:12 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 33/82] target/arm: Implement SVE2 MATCH, NMATCH Richard Henderson
2021-04-30 20:25 ` [PATCH v6 34/82] target/arm: Implement SVE2 saturating multiply-add long Richard Henderson
2021-05-12 14:21 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 35/82] target/arm: Implement SVE2 saturating multiply-add high Richard Henderson
2021-05-12 15:12 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 36/82] target/arm: Implement SVE2 integer multiply-add long Richard Henderson
2021-05-12 15:13 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 37/82] target/arm: Implement SVE2 complex integer multiply-add Richard Henderson
2021-05-12 15:20 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 38/82] target/arm: Implement SVE2 ADDHNB, ADDHNT Richard Henderson
2021-05-12 15:23 ` Peter Maydell
2021-05-12 16:17 ` Richard Henderson
2021-04-30 20:25 ` [PATCH v6 39/82] target/arm: Implement SVE2 RADDHNB, RADDHNT Richard Henderson
2021-05-12 15:24 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 40/82] target/arm: Implement SVE2 SUBHNB, SUBHNT Richard Henderson
2021-05-12 15:24 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 41/82] target/arm: Implement SVE2 RSUBHNB, RSUBHNT Richard Henderson
2021-05-12 15:25 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 42/82] target/arm: Implement SVE2 HISTCNT, HISTSEG Richard Henderson
2021-05-13 10:22 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 43/82] target/arm: Implement SVE2 XAR Richard Henderson
2021-05-13 10:27 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 44/82] target/arm: Implement SVE2 scatter store insns Richard Henderson
2021-05-13 10:31 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 45/82] target/arm: Implement SVE2 gather load insns Richard Henderson
2021-05-13 10:33 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 46/82] target/arm: Implement SVE2 FMMLA Richard Henderson
2021-05-13 10:38 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 47/82] target/arm: Implement SVE2 SPLICE, EXT Richard Henderson
2021-05-13 10:41 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 48/82] target/arm: Pass separate addend to {U, S}DOT helpers Richard Henderson
2021-05-13 10:47 ` Peter Maydell
2021-05-14 16:33 ` Richard Henderson
2021-05-14 16:35 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 49/82] target/arm: Pass separate addend to FCMLA helpers Richard Henderson
2021-04-30 20:25 ` [PATCH v6 50/82] target/arm: Split out formats for 2 vectors + 1 index Richard Henderson
2021-05-13 10:49 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 51/82] target/arm: Split out formats for 3 " Richard Henderson
2021-05-13 10:53 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 52/82] target/arm: Implement SVE2 integer multiply (indexed) Richard Henderson
2021-05-13 12:31 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 53/82] target/arm: Implement SVE2 integer multiply-add (indexed) Richard Henderson
2021-05-13 12:33 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 54/82] target/arm: Implement SVE2 saturating multiply-add high (indexed) Richard Henderson
2021-05-13 12:35 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 55/82] target/arm: Implement SVE2 saturating multiply-add (indexed) Richard Henderson
2021-05-13 12:42 ` Peter Maydell
2021-05-14 18:17 ` Richard Henderson
2021-04-30 20:25 ` [PATCH v6 56/82] target/arm: Implement SVE2 saturating multiply (indexed) Richard Henderson
2021-05-13 12:45 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 57/82] target/arm: Implement SVE2 signed saturating doubling multiply high Richard Henderson
2021-05-13 12:48 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 58/82] target/arm: Implement SVE2 saturating multiply high (indexed) Richard Henderson
2021-05-13 12:51 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 59/82] target/arm: Implement SVE mixed sign dot product (indexed) Richard Henderson
2021-05-13 12:57 ` Peter Maydell
2021-05-14 18:47 ` Richard Henderson
2021-04-30 20:25 ` [PATCH v6 60/82] target/arm: Implement SVE mixed sign dot product Richard Henderson
2021-05-13 13:01 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 61/82] target/arm: Implement SVE2 crypto unary operations Richard Henderson
2021-05-13 13:02 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 62/82] target/arm: Implement SVE2 crypto destructive binary operations Richard Henderson
2021-05-13 13:04 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 63/82] target/arm: Implement SVE2 crypto constructive " Richard Henderson
2021-05-13 13:52 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 64/82] target/arm: Implement SVE2 TBL, TBX Richard Henderson
2021-05-13 13:59 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 65/82] target/arm: Implement SVE2 FCVTNT Richard Henderson
2021-05-13 14:01 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 66/82] target/arm: Implement SVE2 FCVTLT Richard Henderson
2021-05-13 14:03 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 67/82] target/arm: Implement SVE2 FCVTXNT, FCVTX Richard Henderson
2021-05-13 14:06 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 68/82] target/arm: Implement SVE2 FLOGB Richard Henderson
2021-05-13 14:18 ` Peter Maydell
2021-05-15 16:14 ` Richard Henderson
2021-04-30 20:25 ` [PATCH v6 69/82] target/arm: Share table of sve load functions Richard Henderson
2021-05-13 14:25 ` Peter Maydell
2021-05-15 16:25 ` Richard Henderson
2021-04-30 20:25 ` [PATCH v6 70/82] target/arm: Implement SVE2 LD1RO Richard Henderson
2021-05-13 16:41 ` Peter Maydell
2021-04-30 20:25 ` [PATCH v6 71/82] target/arm: Implement 128-bit ZIP, UZP, TRN Richard Henderson
2021-05-13 16:48 ` Peter Maydell
2021-04-30 20:26 ` [PATCH v6 72/82] target/arm: Implement SVE2 bitwise shift immediate Richard Henderson
2021-05-13 16:57 ` Peter Maydell
2021-05-15 16:53 ` Richard Henderson
2021-04-30 20:26 ` [PATCH v6 73/82] target/arm: Implement SVE2 fp multiply-add long Richard Henderson
2021-05-13 17:04 ` Peter Maydell
2021-05-15 17:09 ` Richard Henderson
2021-04-30 20:26 ` [PATCH v6 74/82] target/arm: Implement aarch64 SUDOT, USDOT Richard Henderson
2021-05-13 17:09 ` Peter Maydell
2021-04-30 20:26 ` [PATCH v6 75/82] target/arm: Split out do_neon_ddda_fpst Richard Henderson
2021-05-13 17:13 ` Peter Maydell
2021-04-30 20:26 ` [PATCH v6 76/82] target/arm: Remove unused fpst from VDOT_scalar Richard Henderson
2021-05-13 17:18 ` Peter Maydell
2021-04-30 20:26 ` [PATCH v6 77/82] target/arm: Fix decode for VDOT (indexed) Richard Henderson
2021-05-13 19:25 ` Peter Maydell
2021-05-15 17:13 ` Richard Henderson
2021-05-16 16:09 ` Peter Maydell
2021-05-17 15:48 ` Richard Henderson
2021-05-15 17:20 ` Richard Henderson
2021-04-30 20:26 ` [PATCH v6 78/82] target/arm: Split decode of VSDOT and VUDOT Richard Henderson
2021-05-13 19:27 ` Peter Maydell
2021-04-30 20:26 ` [PATCH v6 79/82] target/arm: Implement aarch32 VSUDOT, VUSDOT Richard Henderson
2021-05-13 19:32 ` Peter Maydell
2021-04-30 20:26 ` [PATCH v6 80/82] target/arm: Implement integer matrix multiply accumulate Richard Henderson
2021-05-13 19:49 ` Peter Maydell
2021-05-14 16:58 ` Richard Henderson
2021-04-30 20:26 ` [PATCH v6 81/82] linux-user/aarch64: Enable hwcap bits for sve2 and related extensions Richard Henderson
2021-05-13 19:33 ` Peter Maydell
2021-04-30 20:26 ` [PATCH v6 82/82] target/arm: Enable SVE2 " Richard Henderson
2021-05-13 19:35 ` Peter Maydell
2021-05-14 17:21 ` Richard Henderson
2021-05-13 19:49 ` [PATCH v6 00/82] target/arm: Implement SVE2 Peter Maydell
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