From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org, groug@kaod.org
Cc: Matheus Ferst <matheus.ferst@eldorado.org.br>,
Richard Henderson <richard.henderson@linaro.org>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
David Gibson <david@gibson.dropbear.id.au>
Subject: [PULL 38/42] target/ppc: Implement cfuged instruction
Date: Thu, 3 Jun 2021 18:22:27 +1000 [thread overview]
Message-ID: <20210603082231.601214-39-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20210603082231.601214-1-david@gibson.dropbear.id.au>
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210601193528.2533031-12-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 4 ++
target/ppc/int_helper.c | 62 ++++++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 12 +++++
4 files changed, 79 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ea9f2a236c..c517b9f025 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -46,6 +46,7 @@ DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
+DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index bc69c70493..d4044d9069 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -87,6 +87,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - @X
ADDI 001110 ..... ..... ................ @D
ADDIS 001111 ..... ..... ................ @D
+## Fixed-Point Logical Instructions
+
+CFUGED 011111 ..... ..... ..... 0011011100 - @X
+
### Move To/From System Register Instructions
SETBC 011111 ..... ..... ----- 0110000000 - @X_bi
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 41f8477d4b..efa833ef64 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -320,6 +320,68 @@ target_ulong helper_popcntb(target_ulong val)
}
#endif
+uint64_t helper_cfuged(uint64_t src, uint64_t mask)
+{
+ /*
+ * Instead of processing the mask bit-by-bit from the most significant to
+ * the least significant bit, as described in PowerISA, we'll handle it in
+ * blocks of 'n' zeros/ones from LSB to MSB. To avoid the decision to use
+ * ctz or cto, we negate the mask at the end of the loop.
+ */
+ target_ulong m, left = 0, right = 0;
+ unsigned int n, i = 64;
+ bool bit = false; /* tracks if we are processing zeros or ones */
+
+ if (mask == 0 || mask == -1) {
+ return src;
+ }
+
+ /* Processes the mask in blocks, from LSB to MSB */
+ while (i) {
+ /* Find how many bits we should take */
+ n = ctz64(mask);
+ if (n > i) {
+ n = i;
+ }
+
+ /*
+ * Extracts 'n' trailing bits of src and put them on the leading 'n'
+ * bits of 'right' or 'left', pushing down the previously extracted
+ * values.
+ */
+ m = (1ll << n) - 1;
+ if (bit) {
+ right = ror64(right | (src & m), n);
+ } else {
+ left = ror64(left | (src & m), n);
+ }
+
+ /*
+ * Discards the processed bits from 'src' and 'mask'. Note that we are
+ * removing 'n' trailing zeros from 'mask', but the logical shift will
+ * add 'n' leading zeros back, so the population count of 'mask' is kept
+ * the same.
+ */
+ src >>= n;
+ mask >>= n;
+ i -= n;
+ bit = !bit;
+ mask = ~mask;
+ }
+
+ /*
+ * At the end, right was ror'ed ctpop(mask) times. To put it back in place,
+ * we'll shift it more 64-ctpop(mask) times.
+ */
+ if (bit) {
+ n = ctpop64(mask);
+ } else {
+ n = 64 - ctpop64(mask);
+ }
+
+ return left | (right >> n);
+}
+
/*****************************************************************************/
/* PowerPC 601 specific instructions (POWER bridge) */
target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong arg2)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 5f9845fa40..50933a3b9d 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -227,3 +227,15 @@ TRANS(SETBC, do_set_bool_cond, false, false)
TRANS(SETBCR, do_set_bool_cond, false, true)
TRANS(SETNBC, do_set_bool_cond, true, false)
TRANS(SETNBCR, do_set_bool_cond, true, true)
+
+static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
--
2.31.1
next prev parent reply other threads:[~2021-06-03 8:46 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-03 8:21 [PULL 00/42] ppc-for-6.1 queue 20210603 David Gibson
2021-06-03 8:21 ` [PULL 01/42] target/ppc: cleaned error_report from ppc_store_sdr1 David Gibson
2021-06-03 8:21 ` [PULL 02/42] target/ppc: moved ppc_store_lpcr and ppc_store_msr to cpu.c David Gibson
2021-06-03 8:21 ` [PULL 03/42] target/ppc: reduce usage of fpscr_set_rounding_mode David Gibson
2021-06-03 8:21 ` [PULL 04/42] target/ppc: removed unnecessary inclusion of helper-proto.h David Gibson
2021-06-03 8:21 ` [PULL 05/42] spapr: Don't hijack current_machine->boot_order David Gibson
2021-06-03 8:21 ` [PULL 06/42] spapr: Fix EEH capability issue on KVM guest for PCI passthru David Gibson
2021-06-03 8:21 ` [PULL 07/42] spapr: nvdimm: Forward declare and move the definitions David Gibson
2021-06-03 8:21 ` [PULL 08/42] spapr: nvdimm: Fix the persistent-memory root node name in device tree David Gibson
2021-06-03 8:21 ` [PULL 09/42] target/ppc: fold ppc_store_ptcr into it's only caller David Gibson
2021-06-03 8:21 ` [PULL 10/42] spapr: Remove stale comment about power-saving LPCR bits David Gibson
2021-06-03 8:22 ` [PULL 11/42] spapr: Set LPCR to current AIL mode when starting a new CPU David Gibson
2021-06-03 8:22 ` [PULL 12/42] target/ppc: used ternary operator when registering MAS David Gibson
2021-06-03 8:22 ` [PULL 13/42] target/ppc: added ifdefs around TCG-only code David Gibson
2021-06-03 8:22 ` [PULL 14/42] target/ppc: created tcg-stub.c file David Gibson
2021-06-03 8:22 ` [PULL 15/42] target/ppc: updated meson.build to support disable-tcg David Gibson
2021-06-03 8:22 ` [PULL 16/42] target/ppc: remove ppc_cpu_dump_statistics David Gibson
2021-06-03 8:22 ` [PULL 17/42] target/ppc: removed mentions to DO_PPC_STATISTICS David Gibson
2021-06-03 8:22 ` [PULL 18/42] monitor: removed cpustats command David Gibson
2021-06-03 8:22 ` [PULL 19/42] ppc/pef.c: initialize cgs->ready in kvmppc_svm_init() David Gibson
2021-06-03 8:22 ` [PULL 20/42] hw/core/cpu: removed cpu_dump_statistics function David Gibson
2021-06-03 8:22 ` [PULL 21/42] HMP: added info cpustats to removed_features.rst David Gibson
2021-06-03 8:22 ` [PULL 22/42] target/ppc: removed GEN_OPCODE decision tree David Gibson
2021-06-03 8:22 ` [PULL 23/42] target/ppc: removed all mentions to PPC_DUMP_CPU David Gibson
2021-06-03 8:22 ` [PULL 24/42] target/ppc: overhauled and moved logic of storing fpscr David Gibson
2021-06-03 8:22 ` [PULL 25/42] target/ppc: powerpc_excp: Move lpes code to where it is used David Gibson
2021-06-03 8:22 ` [PULL 26/42] target/ppc: powerpc_excp: Remove dump_syscall_vectored David Gibson
2021-06-03 8:22 ` [PULL 27/42] target/ppc: powerpc_excp: Consolidade TLB miss code David Gibson
2021-06-03 8:22 ` [PULL 28/42] target/ppc: Introduce macros to check isa extensions David Gibson
2021-06-03 8:22 ` [PULL 29/42] target/ppc: Move page crossing check to ppc_tr_translate_insn David Gibson
2021-06-03 8:22 ` [PULL 30/42] target/ppc: Add infrastructure for prefixed insns David Gibson
2021-06-03 8:22 ` [PULL 31/42] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI David Gibson
2021-06-03 8:22 ` [PULL 32/42] target/ppc: Implement PNOP David Gibson
2021-06-03 8:22 ` [PULL 33/42] target/ppc: Move D/DS/X-form integer loads to decodetree David Gibson
2021-06-03 8:22 ` [PULL 34/42] target/ppc: Implement prefixed integer load instructions David Gibson
2021-06-03 8:22 ` [PULL 35/42] target/ppc: Move D/DS/X-form integer stores to decodetree David Gibson
2021-06-03 8:22 ` [PULL 36/42] target/ppc: Implement prefixed integer store instructions David Gibson
2021-06-03 8:22 ` [PULL 37/42] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions David Gibson
2021-06-03 8:22 ` David Gibson [this message]
2021-06-03 8:22 ` [PULL 39/42] target/ppc: Implement vcfuged instruction David Gibson
2021-06-03 8:22 ` [PULL 40/42] target/ppc: Move addpcis to decodetree David Gibson
2021-06-03 8:22 ` [PULL 41/42] target/ppc: Move cmp/cmpi/cmpl/cmpli " David Gibson
2021-06-03 8:22 ` [PULL 42/42] target/ppc: fix single-step exception regression David Gibson
2021-06-03 9:01 ` [PULL 00/42] ppc-for-6.1 queue 20210603 no-reply
2021-06-03 10:36 ` Peter Maydell
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