From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH 1/2] docs/system: riscv: Fix CLINT name in the sifive_u doc
Date: Sun, 27 Jun 2021 22:28:15 +0800 [thread overview]
Message-ID: <20210627142816.19789-1-bmeng.cn@gmail.com> (raw)
It's Core *Local* Interruptor, not 'Level'.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
docs/system/riscv/sifive_u.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
index 32d0a1b85d..01108b5ecc 100644
--- a/docs/system/riscv/sifive_u.rst
+++ b/docs/system/riscv/sifive_u.rst
@@ -11,7 +11,7 @@ The ``sifive_u`` machine supports the following devices:
* 1 E51 / E31 core
* Up to 4 U54 / U34 cores
-* Core Level Interruptor (CLINT)
+* Core Local Interruptor (CLINT)
* Platform-Level Interrupt Controller (PLIC)
* Power, Reset, Clock, Interrupt (PRCI)
* L2 Loosely Integrated Memory (L2-LIM)
--
2.25.1
next reply other threads:[~2021-06-27 14:29 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-27 14:28 Bin Meng [this message]
2021-06-27 14:28 ` [PATCH 2/2] docs/system: riscv: Add documentation for virt machine Bin Meng
2021-07-02 7:24 ` Alistair Francis
2021-07-05 5:35 ` Alistair Francis
2021-06-28 0:21 ` [PATCH 1/2] docs/system: riscv: Fix CLINT name in the sifive_u doc Alistair Francis
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