From: WANG Xuerui <git@xen0n.name>
To: qemu-devel@nongnu.org
Cc: "WANG Xuerui" <git@xen0n.name>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Laurent Vivier" <laurent@vivier.eu>
Subject: [PATCH v4 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets
Date: Fri, 24 Sep 2021 00:59:14 +0800 [thread overview]
Message-ID: <20210923165939.729081-6-git@xen0n.name> (raw)
In-Reply-To: <20210923165939.729081-1-git@xen0n.name>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 118 +++++++++++++++++++++++++++++++
1 file changed, 118 insertions(+)
create mode 100644 tcg/loongarch64/tcg-target.c.inc
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
new file mode 100644
index 0000000000..42eebef78e
--- /dev/null
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -0,0 +1,118 @@
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
+ *
+ * Based on tcg/riscv/tcg-target.c.inc
+ *
+ * Copyright (c) 2018 SiFive, Inc
+ * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
+ * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
+ * Copyright (c) 2008 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifdef CONFIG_DEBUG_TCG
+static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
+ "zero",
+ "ra",
+ "tp",
+ "sp",
+ "a0",
+ "a1",
+ "a2",
+ "a3",
+ "a4",
+ "a5",
+ "a6",
+ "a7",
+ "t0",
+ "t1",
+ "t2",
+ "t3",
+ "t4",
+ "t5",
+ "t6",
+ "t7",
+ "t8",
+ "r21", /* reserved in the LP64 ABI, hence no ABI name */
+ "s9",
+ "s0",
+ "s1",
+ "s2",
+ "s3",
+ "s4",
+ "s5",
+ "s6",
+ "s7",
+ "s8"
+};
+#endif
+
+static const int tcg_target_reg_alloc_order[] = {
+ /* Registers preserved across calls */
+ /* TCG_REG_S0 reserved for TCG_AREG0 */
+ TCG_REG_S1,
+ TCG_REG_S2,
+ TCG_REG_S3,
+ TCG_REG_S4,
+ TCG_REG_S5,
+ TCG_REG_S6,
+ TCG_REG_S7,
+ TCG_REG_S8,
+ TCG_REG_S9,
+
+ /* Registers (potentially) clobbered across calls */
+ TCG_REG_T0,
+ TCG_REG_T1,
+ TCG_REG_T2,
+ TCG_REG_T3,
+ TCG_REG_T4,
+ TCG_REG_T5,
+ TCG_REG_T6,
+ TCG_REG_T7,
+ TCG_REG_T8,
+
+ /* Argument registers, opposite order of allocation. */
+ TCG_REG_A7,
+ TCG_REG_A6,
+ TCG_REG_A5,
+ TCG_REG_A4,
+ TCG_REG_A3,
+ TCG_REG_A2,
+ TCG_REG_A1,
+ TCG_REG_A0,
+};
+
+static const int tcg_target_call_iarg_regs[] = {
+ TCG_REG_A0,
+ TCG_REG_A1,
+ TCG_REG_A2,
+ TCG_REG_A3,
+ TCG_REG_A4,
+ TCG_REG_A5,
+ TCG_REG_A6,
+ TCG_REG_A7,
+};
+
+static const int tcg_target_call_oarg_regs[] = {
+ TCG_REG_A0,
+ TCG_REG_A1,
+};
--
2.33.0
next prev parent reply other threads:[~2021-09-23 17:06 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-23 16:59 [PATCH v4 00/30] LoongArch64 port of QEMU TCG WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 01/30] elf: Add machine type value for LoongArch WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 02/30] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer WANG Xuerui
2021-09-23 17:53 ` Philippe Mathieu-Daudé
2021-09-23 16:59 ` [PATCH v4 03/30] tcg/loongarch64: Add the tcg-target.h file WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers WANG Xuerui
2021-09-23 16:59 ` WANG Xuerui [this message]
2021-09-23 16:59 ` [PATCH v4 06/30] tcg/loongarch64: Define the operand constraints WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 07/30] tcg/loongarch64: Implement necessary relocation operations WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 08/30] tcg/loongarch64: Implement the memory barrier op WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi WANG Xuerui
2021-09-24 14:52 ` Richard Henderson
2021-09-23 16:59 ` [PATCH v4 10/30] tcg/loongarch64: Implement goto_ptr WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 11/30] tcg/loongarch64: Implement sign-/zero-extension ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 13/30] tcg/loongarch64: Implement deposit/extract ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 15/30] tcg/loongarch64: Implement clz/ctz ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 17/30] tcg/loongarch64: Implement add/sub ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 19/30] tcg/loongarch64: Implement br/brcond ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 20/30] tcg/loongarch64: Implement setcond ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 21/30] tcg/loongarch64: Implement tcg_out_call WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 22/30] tcg/loongarch64: Implement simple load/store ops WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 23/30] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops WANG Xuerui
2021-09-24 14:56 ` Richard Henderson
2021-09-24 15:19 ` WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 24/30] tcg/loongarch64: Implement tcg_target_qemu_prologue WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 25/30] tcg/loongarch64: Implement exit_tb/goto_tb WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 26/30] tcg/loongarch64: Implement tcg_target_init WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 27/30] tcg/loongarch64: Register the JIT WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 28/30] linux-user: Add safe syscall handling for loongarch64 hosts WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler " WANG Xuerui
2021-09-23 16:59 ` [PATCH v4 30/30] configure, meson.build: Mark support " WANG Xuerui
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