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[123.193.74.252]) by smtp.gmail.com with ESMTPSA id z13sm4271680pfq.130.2021.10.15.00.48.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Oct 2021 00:48:56 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended Date: Fri, 15 Oct 2021 15:45:42 +0800 Message-Id: <20211015074627.3957162-42-frank.chang@sifive.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211015074627.3957162-1-frank.chang@sifive.com> References: <20211015074627.3957162-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Palmer Dabbelt , Alistair Francis , Bin Meng , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang For some vector instructions (e.g. vmv.s.x), the element is loaded with sign-extended. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++++++++++++-------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 3751496676f..31ea231b3be 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2824,17 +2824,29 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) /* Integer Extract Instruction */ static void load_element(TCGv_i64 dest, TCGv_ptr base, - int ofs, int sew) + int ofs, int sew, bool sign) { switch (sew) { case MO_8: - tcg_gen_ld8u_i64(dest, base, ofs); + if (!sign) { + tcg_gen_ld8u_i64(dest, base, ofs); + } else { + tcg_gen_ld8s_i64(dest, base, ofs); + } break; case MO_16: - tcg_gen_ld16u_i64(dest, base, ofs); + if (!sign) { + tcg_gen_ld16u_i64(dest, base, ofs); + } else { + tcg_gen_ld16s_i64(dest, base, ofs); + } break; case MO_32: - tcg_gen_ld32u_i64(dest, base, ofs); + if (!sign) { + tcg_gen_ld32u_i64(dest, base, ofs); + } else { + tcg_gen_ld32s_i64(dest, base, ofs); + } break; case MO_64: tcg_gen_ld_i64(dest, base, ofs); @@ -2889,7 +2901,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest, /* Perform the load. */ load_element(dest, base, - vreg_ofs(s, vreg), s->sew); + vreg_ofs(s, vreg), s->sew, false); tcg_temp_free_ptr(base); tcg_temp_free_i32(ofs); @@ -2905,9 +2917,9 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest, } static void vec_element_loadi(DisasContext *s, TCGv_i64 dest, - int vreg, int idx) + int vreg, int idx, bool sign) { - load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew); + load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign); } static bool trans_vext_x_v(DisasContext *s, arg_r *a) @@ -2917,7 +2929,7 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a) if (a->rs1 == 0) { /* Special case vmv.x.s rd, vs2. */ - vec_element_loadi(s, tmp, a->rs2, 0); + vec_element_loadi(s, tmp, a->rs2, 0, false); } else { /* This instruction ignores LMUL and vector register groups */ int vlmax = s->vlen >> (3 + s->sew); @@ -2999,7 +3011,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) (s->mstatus_fs != 0) && (s->sew != 0)) { unsigned int len = 8 << s->sew; - vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0); + vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false); if (len < 64) { tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], MAKE_64BIT_MASK(len, 64 - len)); @@ -3101,7 +3113,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a) TCGv_i64 dest = tcg_temp_new_i64(); if (a->rs1 == 0) { - vec_element_loadi(s, dest, a->rs2, 0); + vec_element_loadi(s, dest, a->rs2, 0, false); } else { vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax); } -- 2.25.1