[RFC 0/5] target/riscv: Add support for BF16 extensions

From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, dbarboza@ventanamicro.com,
	zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
	lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [RFC 0/5] target/riscv: Add support for BF16 extensions
Date: Wed, 12 Apr 2023 10:33:15 +0800	[thread overview]
Message-ID: <20230412023320.50706-1-liweiwei@iscas.ac.cn> (raw)

Specification for BF16 extensions can be found in:
https://github.com/riscv/riscv-bfloat16

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-bf16-upstream

Weiwei Li (5):
  target/riscv: Add properties for BF16 extensions
  target/riscv: Add support for Zfbfmin extension
  target/riscv: Add support for Zvfbfmin extension
  target/riscv: Add support for Zvfbfwma extension
  target/riscv: Expose properties for BF16 extensions

 target/riscv/cpu.c                         |  20 +++
 target/riscv/cpu.h                         |   3 +
 target/riscv/fpu_helper.c                  |  12 ++
 target/riscv/helper.h                      |  10 ++
 target/riscv/insn32.decode                 |  12 ++
 target/riscv/insn_trans/trans_rvbf16.c.inc | 175 +++++++++++++++++++++
 target/riscv/insn_trans/trans_rvzfh.c.inc  |  13 +-
 target/riscv/translate.c                   |   1 +
 target/riscv/vector_helper.c               |  17 ++
 9 files changed, 257 insertions(+), 6 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvbf16.c.inc

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2.25.1